From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A22D3C43217 for ; Mon, 7 Nov 2022 00:56:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230115AbiKGA4J (ORCPT ); Sun, 6 Nov 2022 19:56:09 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:58674 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230079AbiKGA4I (ORCPT ); Sun, 6 Nov 2022 19:56:08 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 7A394A1A7; Sun, 6 Nov 2022 16:56:07 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 63C3513D5; Sun, 6 Nov 2022 16:56:13 -0800 (PST) Received: from slackpad.fritz.box (unknown [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3B2A53F703; Sun, 6 Nov 2022 16:56:05 -0800 (PST) From: Andre Przywara To: Chen-Yu Tsai , Samuel Holland , Jernej Skrabec , Rob Herring , Krzysztof Kozlowski Cc: =?UTF-8?q?Cl=C3=A9ment=20P=C3=A9ron?= , Icenowy Zheng , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, Thierry Reding , =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= , linux-pwm@vger.kernel.org Subject: [PATCH v2 02/10] ARM: dts: suniv: f1c100s: add PWM node Date: Mon, 7 Nov 2022 00:54:25 +0000 Message-Id: <20221107005433.11079-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.35.5 In-Reply-To: <20221107005433.11079-1-andre.przywara@arm.com> References: <20221107005433.11079-1-andre.przywara@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The Allwinner F1C100s family of SoCs contain a PWM controller compatible to the one used in the A20 chip. Add the DT node so that any users can simply enable it in their board DT. Signed-off-by: Andre Przywara --- arch/arm/boot/dts/suniv-f1c100s.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi index a01541ba42c5..81749d5da12f 100644 --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi @@ -218,6 +218,15 @@ wdt: watchdog@1c20ca0 { clocks = <&osc32k>; }; + pwm: pwm@1c21000 { + compatible = "allwinner,suniv-f1c100s-pwm", + "allwinner,sun7i-a20-pwm"; + reg = <0x01c21000 0x400>; + clocks = <&osc24M>; + #pwm-cells = <3>; + status = "disabled"; + }; + uart0: serial@1c25000 { compatible = "snps,dw-apb-uart"; reg = <0x01c25000 0x400>; -- 2.35.5