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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id g92-20020a9d2de5000000b0066c4092ae4csm3272165otb.10.2022.11.07.11.56.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Nov 2022 11:56:57 -0800 (PST) Received: (nullmailer pid 1487934 invoked by uid 1000); Mon, 07 Nov 2022 19:56:59 -0000 Date: Mon, 7 Nov 2022 13:56:59 -0600 From: Rob Herring To: Dinh Nguyen Cc: jh80.chung@samsung.com, ulf.hansson@linaro.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, sboyd@kernel.org, linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org Subject: Re: [PATCHv8 1/6] dt-bindings: mmc: synopsys-dw-mshc: document "altr,sysmgr-syscon" Message-ID: <20221107195659.GA1483239-robh@kernel.org> References: <20221103151525.474833-1-dinguyen@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221103151525.474833-1-dinguyen@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Nov 03, 2022 at 10:15:20AM -0500, Dinh Nguyen wrote: > Document the optional "altr,sysmgr-syscon" binding that is used to > access the System Manager register that controls the SDMMC clock > phase. > > Signed-off-by: Dinh Nguyen > --- > v8: remove "" around synopsys-dw-mshc-common.yaml# > v7: and "not" for the required "altr,sysmgr-syscon" binding > v6: make "altr,sysmgr-syscon" optional > v5: document reg shift > v4: add else statement > v3: document that the "altr,sysmgr-syscon" binding is only applicable to > "altr,socfpga-dw-mshc" > v2: document "altr,sysmgr-syscon" in the MMC section > --- > .../bindings/mmc/synopsys-dw-mshc.yaml | 33 +++++++++++++++++-- > 1 file changed, 30 insertions(+), 3 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > index ae6d6fca79e2..a37cd7a68417 100644 > --- a/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > +++ b/Documentation/devicetree/bindings/mmc/synopsys-dw-mshc.yaml > @@ -6,9 +6,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# > > title: Synopsys Designware Mobile Storage Host Controller Binding > > -allOf: > - - $ref: "synopsys-dw-mshc-common.yaml#" > - > maintainers: > - Ulf Hansson > > @@ -38,6 +35,36 @@ properties: > - const: biu > - const: ciu > > + altr,sysmgr-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle-array > + items: > + - items: > + - description: phandle to the sysmgr node > + - description: register offset that controls the SDMMC clock phase > + - description: register shift for the smplsel(drive in) setting > + description: > + This property is optional. Contains the phandle to System Manager block > + that contains the SDMMC clock-phase control register. The first value is > + the pointer to the sysmgr, the 2nd value is the register offset for the > + SDMMC clock phase register, and the 3rd value is the bit shift for the > + smplsel(drive in) setting. > + > +allOf: > + - $ref: synopsys-dw-mshc-common.yaml# > + > + - if: > + properties: > + compatible: > + contains: > + const: altr,socfpga-dw-mshc > + then: > + not: > + required: > + - altr,sysmgr-syscon 'required' evaluates true when all properties in the list are present. So altr,sysmgr-syscon must not be present. > + else: > + properties: > + altr,sysmgr-syscon: false Else altr,sysmgr-syscon must not be present. ??? Rob