From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 87E21C433FE for ; Fri, 11 Nov 2022 04:57:45 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230043AbiKKE5l (ORCPT ); Thu, 10 Nov 2022 23:57:41 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:49714 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229566AbiKKE5k (ORCPT ); Thu, 10 Nov 2022 23:57:40 -0500 Received: from ams.source.kernel.org (ams.source.kernel.org [145.40.68.75]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F1717671; Thu, 10 Nov 2022 20:57:39 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id A9979B823E9; Fri, 11 Nov 2022 04:57:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 443D4C433D6; Fri, 11 Nov 2022 04:57:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1668142656; bh=Estt/Z+lEYnmR8fT1vRI3VhUQiE2h2Tzj9TxnuhLWJA=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=YtgOMGe3hzVvxxmlcieE/cYs+0zU9SvUXgYaIEA/uXbsENRcvjKw6iYf02ajsXUX+ FJvdPanvvOq3tHSkggDydVpixNz1EaFZ3OaamArPlJVS/nRnxW3fcJ7RE6X3CdomoS IwE316TbuofF7n+E4IV/BLZpB7HU500CanoImoB1lEosu1bw2uXxTClsNemzmC5tez DFNkrZgUhwEtbBvvaizYFhRNy+jbDWYI4mxFJf2XFiHSm4kXduM3ts8yyyS47K8EfU 3USnu9XukFcSvC4fGpS6il9EE+zLEBV70p8OgseltH/o3YxgOo/AqDyV2+bQZuy38w WJgEhBibSTVow== Date: Fri, 11 Nov 2022 12:57:27 +0800 From: Shawn Guo To: Chester Lin Cc: Pierre Gondois , linux-kernel@vger.kernel.org, Rob.Herring@arm.com, Li Yang , Rob Herring , Krzysztof Kozlowski , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , Andreas =?iso-8859-1?Q?F=E4rber?= , Matthias Brugger , NXP S32 Linux Team , Peng Fan , Jacky Bai , Sudeep Holla , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH 07/20] arm64: dts: Update cache properties for freescale Message-ID: <20221111045727.GM125525@dragon> References: <20221031091956.531935-1-pierre.gondois@arm.com> <20221111025553.GJ125525@dragon> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Fri, Nov 11, 2022 at 12:49:08PM +0800, Chester Lin wrote: > Hi Shawn, > > On Fri, Nov 11, 2022 at 10:55:53AM +0800, Shawn Guo wrote: > > On Mon, Oct 31, 2022 at 10:19:51AM +0100, Pierre Gondois wrote: > > > The DeviceTree Specification v0.3 specifies that the cache node > > > 'compatible' and 'cache-level' properties are 'required'. Cf. > > > s3.8 Multi-level and Shared Cache Nodes > > > > > > The recently added init_of_cache_level() function checks > > > these properties. Add them if missing. > > > > > > Signed-off-by: Pierre Gondois > > > > Looks good to me. Should I pick it up on IMX tree, or it needs to go as > > part of the series (via other tree)? > > > > Shawn > > > > The change for s32g2 looks good to me. I would be grateful if you could pick > this patch to the IMX tree. Thanks! > > Reviewed-by: Chester Lin Ok, I will wait a confirmation from Pierre that the intention is indeed for platform maintainer to pick up individual patch. Shawn