From: Manivannan Sadhasivam <mani@kernel.org>
To: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Cc: "Rob Herring" <robh+dt@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzysztof.kozlowski+dt@linaro.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Cai Huoqing" <cai.huoqing@linux.dev>,
"Robin Murphy" <robin.murphy@arm.com>,
"Jingoo Han" <jingoohan1@gmail.com>,
"Gustavo Pimentel" <gustavo.pimentel@synopsys.com>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Serge Semin" <fancer.lancer@gmail.com>,
"Alexey Malahov" <Alexey.Malahov@baikalelectronics.ru>,
"Pavel Parkhomenko" <Pavel.Parkhomenko@baikalelectronics.ru>,
"Frank Li" <Frank.Li@nxp.com>,
"Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
caihuoqing <caihuoqing@baidu.com>,
"Vinod Koul" <vkoul@kernel.org>,
linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v7 18/20] PCI: dwc: Combine iATU detection procedures
Date: Mon, 14 Nov 2022 12:19:31 +0530 [thread overview]
Message-ID: <20221114064931.GF3869@thinkpad> (raw)
In-Reply-To: <20221113191301.5526-19-Sergey.Semin@baikalelectronics.ru>
On Sun, Nov 13, 2022 at 10:12:59PM +0300, Serge Semin wrote:
> Since the iATU CSR region is now retrieved in the DW PCIe resources getter
> there is no much benefits in the iATU detection procedures splitting up.
> Therefore let's join the iATU unroll/viewport detection procedure with the
> rest of the iATU parameters detection code. The resultant method will be
> as coherent as before, while the redundant functions will be eliminated
> thus producing more readable code.
>
> Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> ---
>
> Changelog v3:
> - This is a new patch created on v3 lap of the series.
> ---
> drivers/pci/controller/dwc/pcie-designware.c | 39 +++++---------------
> 1 file changed, 10 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/controller/dwc/pcie-designware.c
> index a8436027434d..d31f9d41d5cb 100644
> --- a/drivers/pci/controller/dwc/pcie-designware.c
> +++ b/drivers/pci/controller/dwc/pcie-designware.c
> @@ -628,26 +628,21 @@ static void dw_pcie_link_set_max_speed(struct dw_pcie *pci, u32 link_gen)
>
> }
>
> -static bool dw_pcie_iatu_unroll_enabled(struct dw_pcie *pci)
> -{
> - u32 val;
> -
> - val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
> - if (val == 0xffffffff)
> - return true;
> -
> - return false;
> -}
> -
> -static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
> +void dw_pcie_iatu_detect(struct dw_pcie *pci)
> {
> int max_region, ob, ib;
> u32 val, min, dir;
> u64 max;
>
> - if (dw_pcie_cap_is(pci, IATU_UNROLL)) {
> + val = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT);
> + if (val == 0xFFFFFFFF) {
> + dw_pcie_cap_set(pci, IATU_UNROLL);
> +
> max_region = min((int)pci->atu_size / 512, 256);
> } else {
> + pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
> + pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
> +
> dw_pcie_writel_dbi(pci, PCIE_ATU_VIEWPORT, 0xFF);
> max_region = dw_pcie_readl_dbi(pci, PCIE_ATU_VIEWPORT) + 1;
> }
> @@ -689,23 +684,9 @@ static void dw_pcie_iatu_detect_regions(struct dw_pcie *pci)
> pci->num_ib_windows = ib;
> pci->region_align = 1 << fls(min);
> pci->region_limit = (max << 32) | (SZ_4G - 1);
> -}
> -
> -void dw_pcie_iatu_detect(struct dw_pcie *pci)
> -{
> - if (dw_pcie_iatu_unroll_enabled(pci)) {
> - dw_pcie_cap_set(pci, IATU_UNROLL);
> - } else {
> - pci->atu_base = pci->dbi_base + PCIE_ATU_VIEWPORT_BASE;
> - pci->atu_size = PCIE_ATU_VIEWPORT_SIZE;
> - }
> -
> - dw_pcie_iatu_detect_regions(pci);
> -
> - dev_info(pci->dev, "iATU unroll: %s\n", dw_pcie_cap_is(pci, IATU_UNROLL) ?
> - "enabled" : "disabled");
>
> - dev_info(pci->dev, "iATU regions: %u ob, %u ib, align %uK, limit %lluG\n",
> + dev_info(pci->dev, "iATU: unroll %s, %u ob, %u ib, align %uK, limit %lluG\n",
> + dw_pcie_cap_is(pci, IATU_UNROLL) ? "T" : "F",
> pci->num_ob_windows, pci->num_ib_windows,
> pci->region_align / SZ_1K, (pci->region_limit + 1) / SZ_1G);
> }
> --
> 2.38.1
>
>
--
மணிவண்ணன் சதாசிவம்
next prev parent reply other threads:[~2022-11-14 6:49 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-11-13 19:12 [PATCH v7 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Serge Semin
2022-11-13 19:12 ` [PATCH v7 01/20] dt-bindings: imx6q-pcie: Fix clock names for imx6sx and imx8mq Serge Semin
2022-11-14 0:06 ` Rob Herring
2022-11-14 11:51 ` Serge Semin
2022-11-16 20:38 ` Rob Herring
2022-11-17 7:43 ` Serge Semin
2022-11-17 7:59 ` Serge Semin
2022-11-13 19:12 ` [PATCH v7 02/20] dt-bindings: visconti-pcie: Fix interrupts array max constraints Serge Semin
2022-11-13 19:12 ` [PATCH v7 03/20] dt-bindings: PCI: dwc: Detach common RP/EP DT bindings Serge Semin
2022-11-13 19:12 ` [PATCH v7 04/20] dt-bindings: PCI: dwc: Remove bus node from the examples Serge Semin
2022-11-13 19:12 ` [PATCH v7 05/20] dt-bindings: PCI: dwc: Add phys/phy-names common properties Serge Semin
2022-11-13 19:12 ` [PATCH v7 06/20] dt-bindings: PCI: dwc: Add max-link-speed common property Serge Semin
2022-11-13 19:12 ` [PATCH v7 07/20] dt-bindings: PCI: dwc: Apply generic schema for generic device only Serge Semin
2022-11-13 19:12 ` [PATCH v7 08/20] dt-bindings: PCI: dwc: Add max-functions EP property Serge Semin
2022-11-13 19:12 ` [PATCH v7 09/20] dt-bindings: PCI: dwc: Add interrupts/interrupt-names common properties Serge Semin
2022-11-13 19:12 ` [PATCH v7 10/20] dt-bindings: PCI: dwc: Add reg/reg-names " Serge Semin
2022-11-13 19:12 ` [PATCH v7 11/20] dt-bindings: PCI: dwc: Add clocks/resets " Serge Semin
2022-11-13 19:12 ` [PATCH v7 12/20] dt-bindings: PCI: dwc: Add dma-coherent property Serge Semin
2022-11-13 19:12 ` [PATCH v7 13/20] dt-bindings: PCI: dwc: Apply common schema to Rockchip DW PCIe nodes Serge Semin
2022-11-13 19:12 ` [PATCH v7 14/20] dt-bindings: PCI: dwc: Add Baikal-T1 PCIe Root Port bindings Serge Semin
2022-11-13 19:12 ` [PATCH v7 15/20] PCI: dwc: Introduce dma-ranges property support for RC-host Serge Semin
2022-11-14 6:39 ` Manivannan Sadhasivam
2022-11-14 8:32 ` Serge Semin
2022-11-14 17:57 ` Manivannan Sadhasivam
2022-11-15 14:17 ` Serge Semin
2022-11-13 19:12 ` [PATCH v7 16/20] PCI: dwc: Introduce generic controller capabilities interface Serge Semin
2022-11-14 6:42 ` Manivannan Sadhasivam
2022-11-13 19:12 ` [PATCH v7 17/20] PCI: dwc: Introduce generic resources getter Serge Semin
2022-11-14 6:46 ` Manivannan Sadhasivam
2022-11-14 8:39 ` Serge Semin
2022-11-14 17:59 ` Manivannan Sadhasivam
2022-11-23 19:44 ` Bjorn Helgaas
2022-11-27 1:10 ` Serge Semin
2022-11-29 18:35 ` Bjorn Helgaas
2022-11-30 0:07 ` Serge Semin
2022-11-13 19:12 ` [PATCH v7 18/20] PCI: dwc: Combine iATU detection procedures Serge Semin
2022-11-14 6:49 ` Manivannan Sadhasivam [this message]
2022-11-13 19:13 ` [PATCH v7 19/20] PCI: dwc: Introduce generic platform clocks and resets Serge Semin
2022-11-14 7:01 ` Manivannan Sadhasivam
2022-11-14 9:37 ` Serge Semin
2022-11-14 18:01 ` Manivannan Sadhasivam
2022-11-13 19:13 ` [PATCH v7 20/20] PCI: dwc: Add Baikal-T1 PCIe controller support Serge Semin
2022-11-14 7:31 ` Manivannan Sadhasivam
2022-11-14 11:20 ` Serge Semin
2022-11-14 18:11 ` Manivannan Sadhasivam
2022-11-15 16:26 ` Serge Semin
2022-11-23 15:09 ` [PATCH v7 00/20] PCI: dwc: Add generic resources and Baikal-T1 support Lorenzo Pieralisi
2022-11-25 12:58 ` Serge Semin
2022-11-25 20:22 ` Serge Semin
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