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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id j59-20020a9d17c1000000b0066da36d2c45sm2641748otj.22.2022.11.16.07.44.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 16 Nov 2022 07:44:06 -0800 (PST) Received: (nullmailer pid 48656 invoked by uid 1000); Wed, 16 Nov 2022 15:44:08 -0000 Date: Wed, 16 Nov 2022 09:44:08 -0600 From: Rob Herring To: Abel Vesa Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , "vkoul@kernel.org" , Kishon Vijay Abraham I , Krzysztof Kozlowski , Linux Kernel Mailing List , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH 08/10] dt-bindings: phy: Add qcom,snps-eusb2-phy schema file Message-ID: <20221116154408.GA4193429-robh@kernel.org> References: <20221116120157.2706810-1-abel.vesa@linaro.org> <20221116120157.2706810-9-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20221116120157.2706810-9-abel.vesa@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Nov 16, 2022 at 02:01:55PM +0200, Abel Vesa wrote: > The SM8550 SoC uses Synopsis eUSB2 PHY. Add a dt-binding schema > for the new driver. > > Signed-off-by: Abel Vesa > --- > .../bindings/phy/qcom,snps-eusb2-phy.yaml | 84 +++++++++++++++++++ > 1 file changed, 84 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml > > diff --git a/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml > new file mode 100644 > index 000000000000..d6a4bdd0cd42 > --- /dev/null > +++ b/Documentation/devicetree/bindings/phy/qcom,snps-eusb2-phy.yaml > @@ -0,0 +1,84 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > + > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/phy/qcom,snps-eusb2-phy.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm SNPS eUSB2 phy controller > + > +maintainers: > + - Abel Vesa > + > +description: > + eUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets. > + > +properties: > + compatible: > + const: qcom,sm8550-snps-eusb2-phy > + > + reg: > + maxItems: 1 > + > + "#phy-cells": > + const: 0 > + > + clocks: > + items: > + - description: ref src parent to 'ref'? If so, parent clocks don't go in 'clocks'. > + - description: ref > + > + clock-names: > + items: > + - const: ref_src > + - const: ref > + > + usb-repeater: > + description: > + Phandle to eUSB2 to USB 2.0 repeater > + > + vdd-supply: > + description: > + Phandle to 0.88V regulator supply to PHY digital circuit. > + > + vdda12-supply: > + description: > + Phandle to 1.2V regulator supply to PHY refclk pll block. > + > + resets: > + maxItems: 1 > + description: > + Phandle to reset to phy block. > + > +required: > + - compatible > + - reg > + - "#phy-cells" > + - clocks > + - clock-names > + - vdd-supply > + - vdda12-supply > + - resets > + > +additionalProperties: false > + > +examples: > + - | > + #include > + #include > + #include > + > + usb_1_hsphy: phy@88e3000 { > + compatible = "qcom,sm8550-snps-eusb2-phy"; > + reg = <0x88e3000 0x154>; > + #phy-cells = <0>; > + > + clocks = <&rpmhcc RPMH_CXO_PAD_CLK>, > + <&tcsrcc TCSR_USB2_CLKREF_EN>; > + clock-names = "ref_src", "ref"; > + > + vdd-supply = <&vreg_l1e_0p88>; > + vdda12-supply = <&vreg_l3e_1p2>; > + > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; > + }; > -- > 2.34.1 > >