From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 77D32C43217 for ; Thu, 17 Nov 2022 13:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234727AbiKQNnc convert rfc822-to-8bit (ORCPT ); Thu, 17 Nov 2022 08:43:32 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:54084 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240187AbiKQNn1 (ORCPT ); Thu, 17 Nov 2022 08:43:27 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id F3E3B748CA; Thu, 17 Nov 2022 05:43:22 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id B5CFE1063; Thu, 17 Nov 2022 05:43:28 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D202F3F663; Thu, 17 Nov 2022 05:43:20 -0800 (PST) Date: Thu, 17 Nov 2022 13:43:18 +0000 From: Andre Przywara To: Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= Cc: Jernej Skrabec , Samuel Holland , Chen-Yu Tsai , Rob Herring , Krzysztof Kozlowski , devicetree@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, Icenowy Zheng , Thierry Reding , linux-pwm@vger.kernel.org Subject: Re: [PATCH 2/9] ARM: dts: suniv: f1c100s: add PWM node Message-ID: <20221117134318.5d40acc1@donnerap.cambridge.arm.com> In-Reply-To: <20221117120350.kreyg7an5dtuaudr@pengutronix.de> References: <20221101141658.3631342-1-andre.przywara@arm.com> <20221101141658.3631342-3-andre.przywara@arm.com> <20221117120350.kreyg7an5dtuaudr@pengutronix.de> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8BIT Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, 17 Nov 2022 13:03:50 +0100 Uwe Kleine-König wrote: Hi Uwe, > On Tue, Nov 01, 2022 at 02:16:51PM +0000, Andre Przywara wrote: > > The Allwinner F1C100s family of SoCs contain a PWM controller compatible > > to the one used in the A20 chip. > > Add the DT node so that any users can simply enable it in their board > > DT. > > > > Signed-off-by: Andre Przywara > > Acked-by: Uwe Kleine-König > > I assume this patch will go via an architecture tree (i.e. not PWM). Yes, still the same as in the v2 that you already acked ;-) In fact the patches are in today's -next already. Cheers, Andre