From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9DC8CC43217 for ; Sat, 19 Nov 2022 04:09:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231764AbiKSEJt (ORCPT ); Fri, 18 Nov 2022 23:09:49 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:60798 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231308AbiKSEJl (ORCPT ); Fri, 18 Nov 2022 23:09:41 -0500 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 3F1A77343B; Fri, 18 Nov 2022 20:09:40 -0800 (PST) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 2AJ49ARp042790; Fri, 18 Nov 2022 22:09:10 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1668830950; bh=Z8xRJ/qJAgGwaqcbsQEUnh9fo1oZl8ZZMTwIII+I9yw=; h=From:To:CC:Subject:Date; b=jCqS0xXATHFN429IALwBVutJpVG6pvZrZhrkn1Xwrw/sutNQIEcuJ4JwMfaN+Cegf excvjaD2gThZ5QmZ66aSaOKMqxMjyH19rbVnkLrTt9HhyrnatP+ocDTG8pnLddvqgD pJ9M2h8V/gcWLYjSaINV3fmuyuTnDyerJeUeRBjw= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 2AJ49ApP002047 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Nov 2022 22:09:10 -0600 Received: from DLEE114.ent.ti.com (157.170.170.25) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Fri, 18 Nov 2022 22:09:10 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Fri, 18 Nov 2022 22:09:10 -0600 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 2AJ497Po118516; Fri, 18 Nov 2022 22:09:09 -0600 From: Matt Ranostay To: , , , , , , CC: , , Subject: [PATCH v6 0/8] J721S2: Add support for additional IPs Date: Fri, 18 Nov 2022 20:08:58 -0800 Message-ID: <20221119040906.9495-1-mranostay@ti.com> X-Mailer: git-send-email 2.38.GIT MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The following series of patches add support for the following on J721S2 common processor board, - USB - SerDes - OSPI - PCIe Changes from v1: * Resolve issues with dt schema reporting * Minor changes related to consistency on node naming and value Changes from v2: * Added PCIe RC + EP enablement patchsets * Added device-id for j722s2 PCIe host in dt documentation * Reworked SERDES + WIZ enablement patchset to use properies for clocks defines versus entire devicetree nodes. Results in cleaner code that doesn't break dt-schema or the driver functionality. Changes from v3: * Rebased changes on top of '[PATCH 00/12] TI J7x Disable Incomplete DT Nodes' * Removed "dt-bindings: PCI: Add host mode device-id for j721s2 platform" patch and send it own series to avoid a dependency that would hold up other patches in this series Changes from v4: * Add my Signed-off-by lines to all patchsets Changes from v5: * Removed Cc from commit messages to reduce clutter * Squashed changes for device tree nodes that get modified latter in the patchset series Aswath Govindraju (7): arm64: dts: ti: k3-j721s2-main: Add support for USB arm64: dts: ti: k3-j721s2-mcu-wakeup: Add support of OSPI arm64: dts: ti: k3-j721s2-common-proc-board: Enable SERDES0 arm64: dts: ti: k3-j721s2-common-proc-board: Add USB support arm64: dts: ti: k3-j721s2: Add support for OSPI Flashes arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe Matt Ranostay (1): arm64: dts: ti: k3-j721s2-main: Add SERDES and WIZ device tree node .../dts/ti/k3-j721s2-common-proc-board.dts | 92 ++++++++++ arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 157 ++++++++++++++++++ .../boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 40 +++++ arch/arm64/boot/dts/ti/k3-j721s2-som-p0.dtsi | 42 +++++ 4 files changed, 331 insertions(+) -- 2.38.GIT