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From: Yu Tu <yu.tu@amlogic.com>
To: <linux-clk@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-amlogic@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Neil Armstrong <narmstrong@linaro.org>,
	Jerome Brunet <jbrunet@baylibre.com>,
	Kevin Hilman <khilman@baylibre.com>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: <kelvin.zhang@amlogic.com>, Yu Tu <yu.tu@amlogic.com>
Subject: [PATCH V5 2/4] arm64: dts: meson: add S4 Soc PLL clock controller in DT
Date: Wed, 23 Nov 2022 10:13:44 +0800	[thread overview]
Message-ID: <20221123021346.18136-3-yu.tu@amlogic.com> (raw)
In-Reply-To: <20221123021346.18136-1-yu.tu@amlogic.com>

Added information about the S4 SOC PLL Clock controller in DT.

Signed-off-by: Yu Tu <yu.tu@amlogic.com>
---
 arch/arm64/boot/dts/amlogic/meson-s4.dtsi | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
index ad50cba42d19..bd9c2ef83314 100644
--- a/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-s4.dtsi
@@ -92,6 +92,14 @@ apb4: apb4@fe000000 {
 			#size-cells = <2>;
 			ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x480000>;
 
+			clkc_pll: clock-controller@8000 {
+				compatible = "amlogic,s4-pll-clkc";
+				reg = <0x0 0x8000 0x0 0x1e8>;
+				clocks = <&xtal>;
+				clock-names = "xtal";
+				#clock-cells = <1>;
+			};
+
 			periphs_pinctrl: pinctrl@4000 {
 				compatible = "amlogic,meson-s4-periphs-pinctrl";
 				#address-cells = <2>;
-- 
2.33.1


  parent reply	other threads:[~2022-11-23  2:16 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-11-23  2:13 [PATCH V5 0/4] Add S4 SoC PLL and Peripheral clock controller Yu Tu
2022-11-23  2:13 ` [PATCH V5 1/4] clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver and bindings Yu Tu
2022-11-23 10:08   ` Krzysztof Kozlowski
2022-11-23 11:16     ` Yu Tu
2022-11-23 13:05       ` Krzysztof Kozlowski
2022-11-23 13:23       ` Neil Armstrong
2022-11-23 13:53         ` Krzysztof Kozlowski
2022-11-25  9:23           ` Jerome Brunet
2022-11-28  7:39             ` Yu Tu
2022-11-28 12:33               ` Jerome Brunet
2022-11-28 13:30                 ` Yu Tu
2022-12-01  8:36                   ` neil.armstrong
2022-12-01 11:33                     ` Yu Tu
2022-11-23 13:54         ` Yu Tu
2022-11-23 13:57           ` neil.armstrong
2022-11-23  2:13 ` Yu Tu [this message]
2022-11-23  2:13 ` [PATCH V5 3/4] clk: meson: s4: add s4 SoC peripheral clock controller " Yu Tu
2022-11-23 10:09   ` Krzysztof Kozlowski
2022-11-23 11:22     ` Yu Tu
2022-11-23 13:06       ` Krzysztof Kozlowski
2022-11-23 14:08         ` Yu Tu
2022-11-25  9:54   ` Jerome Brunet
2022-11-28  8:08     ` Yu Tu
2022-11-28 12:23       ` Jerome Brunet
2022-11-28 14:02         ` Yu Tu
2022-11-23  2:13 ` [PATCH V5 4/4] arm64: dts: meson: add S4 Soc Peripheral clock controller in DT Yu Tu
2022-11-23 10:10   ` Krzysztof Kozlowski
2022-11-23 11:27     ` Yu Tu
2022-11-23 13:02       ` Krzysztof Kozlowski
2022-11-23 13:23         ` Yu Tu
2022-11-23 14:12           ` Krzysztof Kozlowski
2022-11-23 14:23             ` Yu Tu
2022-11-23 13:27     ` Neil Armstrong
2022-11-23 13:38       ` Yu Tu
2022-11-23 14:13       ` Krzysztof Kozlowski
2022-11-23 14:21         ` neil.armstrong
2022-11-23 14:27           ` Yu Tu

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