From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A7C7DC4332F for ; Wed, 23 Nov 2022 10:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236662AbiKWKZ6 (ORCPT ); Wed, 23 Nov 2022 05:25:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48442 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236695AbiKWKYy (ORCPT ); Wed, 23 Nov 2022 05:24:54 -0500 Received: from us-smtp-delivery-115.mimecast.com (us-smtp-delivery-115.mimecast.com [170.10.133.115]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8C0153FB86 for ; Wed, 23 Nov 2022 02:09:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=maxlinear.com; s=selector; t=1669198159; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Mc2NS0olCt0qUzsLi0zWfYaDeL0jAmHwQjCqJZ5SsT8=; b=L+GVyjPqXoUVb88eR1PLWSrDEGisi7H/3q53bDnpq89e5lQotXDQ1q9XxB/f9VBcgC36gj +ifynGzJb3ap2gtkXeOZe8YNXcu2XHay0rEaOMzVyNBdwaexjsbLM6rrQzl3e4KjD/KVAM 341L0QKw3RNRA70L+Vk5zTQ21znytj55rAwBavs5m2QZwgQcXEyLZjCIUetXuDJuL31mmc gMVHMzYdY+h/4nzahvN97tq3G6uUivZ75Wm39jUhIi3gXOV2eNc7YNxVobQQgy+KXj1Tkb TIhiD6Ynopk0aGqe+BmZ2HcZjTzqZKAN2Y6GE4p0c9lw4NM2LZ2nB9N+FmyMXQ== Received: from mail.maxlinear.com (174-47-1-84.static.ctl.one [174.47.1.84]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id us-mta-60-BskRCc8PMByVuKyULDY1HA-1; Wed, 23 Nov 2022 05:09:16 -0500 X-MC-Unique: BskRCc8PMByVuKyULDY1HA-1 Received: from sgsxdev001.isng.phoenix.local (10.226.81.111) by mail.maxlinear.com (10.23.38.119) with Microsoft SMTP Server id 15.1.2375.24; Wed, 23 Nov 2022 02:09:08 -0800 From: Rahul Tanwar To: Rahul Tanwar , , CC: Thomas Gleixner , Marc Zyngier , "Rob Herring" , Krzysztof Kozlowski , Ingo Molnar , "Borislav Petkov" , Dave Hansen , , "H. Peter Anvin" , , Subject: [PATCH v4 4/4] x86/of: Add support for boot time interrupt delivery mode configuration Date: Wed, 23 Nov 2022 18:08:50 +0800 Message-ID: <20221123100850.22969-5-rtanwar@maxlinear.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20221123100850.22969-1-rtanwar@maxlinear.com> References: <20221123100850.22969-1-rtanwar@maxlinear.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: maxlinear.com Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Presently, init/boot time interrupt delivery mode is enumerated only for ACPI enabled systems by parsing MADT table or for older systems by parsing MP table. But for OF based x86 systems, it is assumed & hardcoded to legacy PIC mode. This causes boot time crash for platforms which do not use 8259 compliant legacy PIC. Add support for configuration of init time interrupt delivery mode for x86 OF based systems by introducing a new optional boolean property 'intel,virtual-wire-mode' for interrupt-controller node of local APIC. This property emulates IMCRP Bit 7 of MP feature info byte 2 of MP floating pointer structure. Defaults to legacy PIC mode if absent. Configures it to virtual wire compatibility mode if present. Signed-off-by: Rahul Tanwar --- arch/x86/kernel/devicetree.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/devicetree.c b/arch/x86/kernel/devicetree.c index fcc6f1b7818f..458e43490414 100644 --- a/arch/x86/kernel/devicetree.c +++ b/arch/x86/kernel/devicetree.c @@ -167,7 +167,14 @@ static void __init dtb_lapic_setup(void) =09=09=09return; =09} =09smp_found_config =3D 1; -=09pic_mode =3D 1; +=09if (of_property_read_bool(dn, "intel,virtual-wire-mode")) { +=09=09pr_info("Virtual Wire compatibility mode.\n"); +=09=09pic_mode =3D 0; +=09} else { +=09=09pr_info("IMCR and PIC compatibility mode.\n"); +=09=09pic_mode =3D 1; +=09} + =09register_lapic_address(lapic_addr); } =20 --=20 2.17.1