From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4BC62C43217 for ; Thu, 24 Nov 2022 13:06:52 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230048AbiKXNGv (ORCPT ); Thu, 24 Nov 2022 08:06:51 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57710 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230056AbiKXNGr (ORCPT ); Thu, 24 Nov 2022 08:06:47 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id D8E721025CA; Thu, 24 Nov 2022 05:06:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669295206; x=1700831206; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=jkht1lqZ+yao+3lR7ZjiS5rsmbUp+VlY/aGj4tz6xiw=; b=vZSRB/vrqLIKAW0wvTSHPdSH/gGIgAcFy/pmppL0b/Szcidir6NFsiKN ZXqDcOTXy/jDGZwPXRPM84EP5lO482xaxpzmAlmjEiRmLqFD0DZEY5P3n q+nu4nvLZM2d4VHwxVfb8ig2gPG3RnlIv73gpw3E/sAyuqf8T+CbRfCkQ J9X+Npl5xG+M8XsqVru6v7Zv76hLm5hnbCNuq6fKfvXxtsYbRwgO6RQrx ooEJTlXcnyKhJl111zYNPiZgZTfI+V1elQ9EZU+NhL6jSeM5o6sDav7Os jIDbf37vl0t+bzW00IvBx/r9YAqLTnveBt1DSsGIGzDaieq2uI/FSyYEN A==; X-IronPort-AV: E=Sophos;i="5.96,190,1665471600"; d="scan'208";a="185029556" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 24 Nov 2022 06:06:45 -0700 Received: from chn-vm-ex02.mchp-main.com (10.10.85.144) by chn-vm-ex01.mchp-main.com (10.10.85.143) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Thu, 24 Nov 2022 06:06:44 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Thu, 24 Nov 2022 06:06:42 -0700 From: Conor Dooley To: CC: Conor Dooley , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Paul Walmsley , Palmer Dabbelt , Albert Ou , Heiko Stuebner , Andrew Jones , Guo Ren , , Subject: [PATCH 1/2] dt-bindings: riscv: fix underscore requirement for addtional standard extensions Date: Thu, 24 Nov 2022 13:04:40 +0000 Message-ID: <20221124130440.306771-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: <20221124130440.306771-1-conor.dooley@microchip.com> References: <20221124130440.306771-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The RISC-V ISA Manual allows for the first Additional Standard Extension having no leading underscore. Only if there are multiple Additional Standard Extensions is it needed to have an underscore. The dt-binding does not validate that a multi-letter extension is canonically ordered, as that'd need an even worse regex than is here, but it should not fail validation for valid ISA strings. Allow the first Z multi-letter extension to appear immediately prior after the single-letter extensions. Link: https://github.com/riscv/riscv-isa-manual/releases/tag/riscv-unpriv-pdf-from-asciidoc-15112022 # Chapter 29.5 Fixes: 299824e68bd0 ("dt-bindings: riscv: add new riscv,isa strings for emulators") Signed-off-by: Conor Dooley --- Documentation/devicetree/bindings/riscv/cpus.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 90a7cabf58fe..e80c967a4fa4 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -80,7 +80,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase to simplify parsing. $ref: "/schemas/types.yaml#/definitions/string" - pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?v?k?h?(?:z(?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ # RISC-V requires 'timebase-frequency' in /cpus, so disallow it here timebase-frequency: false -- 2.38.1