* [PATCH v3 0/2] arm/arm64: dts: Update cache properties for broadcom
@ 2022-11-22 16:32 Pierre Gondois
2022-11-22 16:32 ` [PATCH v3 1/2] arm: " Pierre Gondois
2022-11-22 16:32 ` [PATCH v3 2/2] arm64: " Pierre Gondois
0 siblings, 2 replies; 5+ messages in thread
From: Pierre Gondois @ 2022-11-22 16:32 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, William Zhang, Anand Gore, Kursad Oney,
Rafał Miłecki, devicetree, linux-rpi-kernel,
linux-arm-kernel
This patch is the v3 of the update of broadcom dts:
https://lore.kernel.org/all/20221107155825.1644604-7-pierre.gondois@arm.com/
v3:
- Update the missed dtsi: bcm2836.dtsi, bcm47622.dtsi, bcm63148.dtsi,
bcm63178.dtsi, bcm6756.dtsi, bcm6846.dtsi, bcm6855.dtsi, bcm6878.dtsi
- Split the patch between arch/[arm|arm64] folders
Note:
As the 'cache-unified' property is only required by the DT spec when there
is one of these properties in the cache node:
'cache-[size|line-size|block-size|sets|level]'
the 'cache-unified' property was added only when necessary, cf:
https://lore.kernel.org/all/433efe6b-858f-6777-0f46-fdf4f4a7e0ca@arm.com/#t
Pierre Gondois (2):
arm: dts: Update cache properties for broadcom
arm64: dts: Update cache properties for broadcom
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2836.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm/boot/dts/bcm47622.dtsi | 1 +
arch/arm/boot/dts/bcm63148.dtsi | 1 +
arch/arm/boot/dts/bcm63178.dtsi | 1 +
arch/arm/boot/dts/bcm6756.dtsi | 1 +
arch/arm/boot/dts/bcm6846.dtsi | 1 +
arch/arm/boot/dts/bcm6855.dtsi | 1 +
arch/arm/boot/dts/bcm6878.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
19 files changed, 22 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 1/2] arm: dts: Update cache properties for broadcom
2022-11-22 16:32 [PATCH v3 0/2] arm/arm64: dts: Update cache properties for broadcom Pierre Gondois
@ 2022-11-22 16:32 ` Pierre Gondois
2022-11-28 23:37 ` Florian Fainelli
2022-11-22 16:32 ` [PATCH v3 2/2] arm64: " Pierre Gondois
1 sibling, 1 reply; 5+ messages in thread
From: Pierre Gondois @ 2022-11-22 16:32 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, William Zhang, Anand Gore, Kursad Oney,
Rafał Miłecki, devicetree, linux-rpi-kernel,
linux-arm-kernel
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 1 +
arch/arm/boot/dts/bcm2836.dtsi | 1 +
arch/arm/boot/dts/bcm2837.dtsi | 1 +
arch/arm/boot/dts/bcm47622.dtsi | 1 +
arch/arm/boot/dts/bcm63148.dtsi | 1 +
arch/arm/boot/dts/bcm63178.dtsi | 1 +
arch/arm/boot/dts/bcm6756.dtsi | 1 +
arch/arm/boot/dts/bcm6846.dtsi | 1 +
arch/arm/boot/dts/bcm6855.dtsi | 1 +
arch/arm/boot/dts/bcm6878.dtsi | 1 +
10 files changed, 10 insertions(+)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 941c4d16791b..c6104149f959 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -536,6 +536,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x100000>;
cache-line-size = <64>;
cache-sets = <1024>; // 1MiB(size)/64(line-size)=16384ways/16-way set
diff --git a/arch/arm/boot/dts/bcm2836.dtsi b/arch/arm/boot/dts/bcm2836.dtsi
index 534dacfc4dd5..547ecc210f18 100644
--- a/arch/arm/boot/dts/bcm2836.dtsi
+++ b/arch/arm/boot/dts/bcm2836.dtsi
@@ -113,6 +113,7 @@ v7_cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <1024>; // 512KiB(size)/64(line-size)=8192ways/8-way set
diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 5dbdebc46259..b352ac784af6 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -115,6 +115,7 @@ cpu3: cpu@3 {
*/
l2: l2-cache0 {
compatible = "cache";
+ cache-unified;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
diff --git a/arch/arm/boot/dts/bcm47622.dtsi b/arch/arm/boot/dts/bcm47622.dtsi
index 2df04528af82..f4b2db9bc4ab 100644
--- a/arch/arm/boot/dts/bcm47622.dtsi
+++ b/arch/arm/boot/dts/bcm47622.dtsi
@@ -51,6 +51,7 @@ CA7_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm63148.dtsi b/arch/arm/boot/dts/bcm63148.dtsi
index df5307b6b3af..7cd55d64de71 100644
--- a/arch/arm/boot/dts/bcm63148.dtsi
+++ b/arch/arm/boot/dts/bcm63148.dtsi
@@ -35,6 +35,7 @@ B15_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm63178.dtsi b/arch/arm/boot/dts/bcm63178.dtsi
index cbd094dde6d0..043e699cbc27 100644
--- a/arch/arm/boot/dts/bcm63178.dtsi
+++ b/arch/arm/boot/dts/bcm63178.dtsi
@@ -43,6 +43,7 @@ CA7_2: cpu@2 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm6756.dtsi b/arch/arm/boot/dts/bcm6756.dtsi
index ce1b59faf800..5c72219bc194 100644
--- a/arch/arm/boot/dts/bcm6756.dtsi
+++ b/arch/arm/boot/dts/bcm6756.dtsi
@@ -51,6 +51,7 @@ CA7_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm6846.dtsi b/arch/arm/boot/dts/bcm6846.dtsi
index 8aa47a2583b2..81513a793815 100644
--- a/arch/arm/boot/dts/bcm6846.dtsi
+++ b/arch/arm/boot/dts/bcm6846.dtsi
@@ -35,6 +35,7 @@ CA7_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm6855.dtsi b/arch/arm/boot/dts/bcm6855.dtsi
index 620f51aee1a2..5fa5feac0e29 100644
--- a/arch/arm/boot/dts/bcm6855.dtsi
+++ b/arch/arm/boot/dts/bcm6855.dtsi
@@ -43,6 +43,7 @@ CA7_2: cpu@2 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm/boot/dts/bcm6878.dtsi b/arch/arm/boot/dts/bcm6878.dtsi
index 1e8b5fa96c25..4ec836ac4baf 100644
--- a/arch/arm/boot/dts/bcm6878.dtsi
+++ b/arch/arm/boot/dts/bcm6878.dtsi
@@ -35,6 +35,7 @@ CA7_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 1/2] arm: dts: Update cache properties for broadcom
2022-11-22 16:32 ` [PATCH v3 1/2] arm: " Pierre Gondois
@ 2022-11-28 23:37 ` Florian Fainelli
0 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2022-11-28 23:37 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Pierre Gondois, linux-kernel
Cc: Rob Herring, Krzysztof Kozlowski, Ray Jui, Scott Branden,
William Zhang, Anand Gore, Kursad Oney, Rafał Miłecki,
devicetree, linux-rpi-kernel, linux-arm-kernel
On Tue, 22 Nov 2022 17:32:06 +0100, Pierre Gondois <pierre.gondois@arm.com> wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 5+ messages in thread
* [PATCH v3 2/2] arm64: dts: Update cache properties for broadcom
2022-11-22 16:32 [PATCH v3 0/2] arm/arm64: dts: Update cache properties for broadcom Pierre Gondois
2022-11-22 16:32 ` [PATCH v3 1/2] arm: " Pierre Gondois
@ 2022-11-22 16:32 ` Pierre Gondois
2022-11-28 23:37 ` Florian Fainelli
1 sibling, 1 reply; 5+ messages in thread
From: Pierre Gondois @ 2022-11-22 16:32 UTC (permalink / raw)
To: linux-kernel
Cc: Pierre Gondois, William Zhang, Rob Herring, Krzysztof Kozlowski,
Florian Fainelli, Broadcom internal kernel review list, Ray Jui,
Scott Branden, Anand Gore, Kursad Oney, Rafał Miłecki,
devicetree, linux-rpi-kernel, linux-arm-kernel
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
Acked-by: William Zhang <william.zhang@broadcom.com>
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
---
arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi | 1 +
arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi | 1 +
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi | 1 +
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi | 4 ++++
9 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
index dac9d3b4e91d..996412ed52a0 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4908.dtsi
@@ -63,6 +63,7 @@ cpu3: cpu@3 {
l2: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
index 3d016c2ce675..d5bc31980f03 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm4912.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
index 04de96bd0a03..6f805266d3c9 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63146.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
index 13629702f70b..b982249b80a2 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm63158.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
index c3e6197be808..a996d436e977 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6813.dtsi
@@ -51,6 +51,7 @@ B53_3: cpu@3 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
index 0bce6497219f..62c530d4b103 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6856.dtsi
@@ -35,6 +35,7 @@ B53_1: cpu@1 {
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
index 29a880c6c858..ba3d5a98ccbc 100644
--- a/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
+++ b/arch/arm64/boot/dts/broadcom/bcmbca/bcm6858.dtsi
@@ -50,6 +50,7 @@ B53_3: cpu@3 {
};
L2_0: l2-cache0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
index fda97c47f4e9..18cdbc20f03f 100644
--- a/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
+++ b/arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
@@ -79,6 +79,7 @@ A57_3: cpu@3 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
};
diff --git a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
index 8f8c25e51194..e05901abe957 100644
--- a/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
+++ b/arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
@@ -108,18 +108,22 @@ cpu@301 {
CLUSTER0_L2: l2-cache@0 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER1_L2: l2-cache@100 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER2_L2: l2-cache@200 {
compatible = "cache";
+ cache-level = <2>;
};
CLUSTER3_L2: l2-cache@300 {
compatible = "cache";
+ cache-level = <2>;
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH v3 2/2] arm64: dts: Update cache properties for broadcom
2022-11-22 16:32 ` [PATCH v3 2/2] arm64: " Pierre Gondois
@ 2022-11-28 23:37 ` Florian Fainelli
0 siblings, 0 replies; 5+ messages in thread
From: Florian Fainelli @ 2022-11-28 23:37 UTC (permalink / raw)
To: bcm-kernel-feedback-list, Pierre Gondois, linux-kernel
Cc: William Zhang, Rob Herring, Krzysztof Kozlowski, Ray Jui,
Scott Branden, Anand Gore, Kursad Oney, Rafał Miłecki,
devicetree, linux-rpi-kernel, linux-arm-kernel
On Tue, 22 Nov 2022 17:32:07 +0100, Pierre Gondois <pierre.gondois@arm.com> wrote:
> The DeviceTree Specification v0.3 specifies that the cache node
> 'compatible' and 'cache-level' properties are 'required'. Cf.
> s3.8 Multi-level and Shared Cache Nodes
> The 'cache-unified' property should be present if one of the
> properties for unified cache is present ('cache-size', ...).
>
> Update the Device Trees accordingly.
>
> Acked-by: William Zhang <william.zhang@broadcom.com>
> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree-arm64/next, thanks!
--
Florian
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-11-28 23:38 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
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2022-11-22 16:32 [PATCH v3 0/2] arm/arm64: dts: Update cache properties for broadcom Pierre Gondois
2022-11-22 16:32 ` [PATCH v3 1/2] arm: " Pierre Gondois
2022-11-28 23:37 ` Florian Fainelli
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