From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 432C2C4321E for ; Tue, 29 Nov 2022 14:51:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234899AbiK2OvZ (ORCPT ); Tue, 29 Nov 2022 09:51:25 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57904 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234622AbiK2OvX (ORCPT ); Tue, 29 Nov 2022 09:51:23 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0601FB4F; Tue, 29 Nov 2022 06:51:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1669733483; x=1701269483; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Ag9tRag2tCMnYNZ7PXKJUn99ayga3IWCVtRNMuIqp7c=; b=TWVfXd706Az1RcBgR0msPdvL/N1kWL128Qm5KnDIZhnwRjjCEVQfRMDt 33gO6eIC+OE5006Jmf7XzpKo8sCIbQcgZ6gKqzkY2MmxJAXW/wRhFH0P7 VjLGUW3NdZ9pC/8gSmvCW60tEengyAJEjm/ByOrxRrKM2jUOimx6LdaGo 8HQUDIkAJXwerZuwKWQ01wlBOUNMOGCZudCGIxzBkaFi2bm1DsNaDXXXU wf0hMGueM37LhaqJDzB4ps9hlprfuBl2PdfBhuTqfMKKZnEhfua7GVm3i 6HvDH72gZSAQXXJJEJvpsjxjCXKwI7w4Firzl79CeA6SJLxGi4lGHaPZy A==; X-IronPort-AV: E=Sophos;i="5.96,203,1665471600"; d="scan'208";a="185697717" Received: from unknown (HELO email.microchip.com) ([170.129.1.10]) by esa4.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 29 Nov 2022 07:51:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex02.mchp-main.com (10.10.85.144) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.12; Tue, 29 Nov 2022 07:51:18 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2507.12 via Frontend Transport; Tue, 29 Nov 2022 07:51:16 -0700 From: Conor Dooley To: CC: Conor Dooley , , , , , , , , , , , Subject: [RFC 2/2] RISC-V: resort all extensions in "canonical" order Date: Tue, 29 Nov 2022 14:47:43 +0000 Message-ID: <20221129144742.2935581-3-conor.dooley@microchip.com> X-Mailer: git-send-email 2.38.1 In-Reply-To: References: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Per the comment in cpu.c, re-sort all lists/tables/enums/whatever in arch/riscv (apart from KVM) in the current edition of what the isa manual considers to be "canonical" order. None of this is in uapi, so we are free to re-order it? I'm never sure when it comes to hwcap... Signed-off-by: Conor Dooley --- arch/riscv/include/asm/hwcap.h | 6 +++--- arch/riscv/kernel/cpu.c | 4 ++-- arch/riscv/kernel/cpufeature.c | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h index b22525290073..d7d5f27619ee 100644 --- a/arch/riscv/include/asm/hwcap.h +++ b/arch/riscv/include/asm/hwcap.h @@ -53,12 +53,12 @@ extern unsigned long elf_hwcap; * available logical extension id. */ enum riscv_isa_ext_id { - RISCV_ISA_EXT_SSCOFPMF = RISCV_ISA_EXT_BASE, - RISCV_ISA_EXT_SVPBMT, - RISCV_ISA_EXT_ZICBOM, + RISCV_ISA_EXT_ZICBOM = RISCV_ISA_EXT_BASE, RISCV_ISA_EXT_ZIHINTPAUSE, + RISCV_ISA_EXT_SSCOFPMF, RISCV_ISA_EXT_SSTC, RISCV_ISA_EXT_SVINVAL, + RISCV_ISA_EXT_SVPBMT, RISCV_ISA_EXT_ID_MAX = RISCV_ISA_EXT_MAX, }; diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c index 5e42c92a8456..1d0fa0ebf6a8 100644 --- a/arch/riscv/kernel/cpu.c +++ b/arch/riscv/kernel/cpu.c @@ -150,12 +150,12 @@ device_initcall(riscv_cpuinfo_init); * extensions by an underscore. */ static struct riscv_isa_ext_data isa_ext_arr[] = { + __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), + __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF), __RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC), __RISCV_ISA_EXT_DATA(svinval, RISCV_ISA_EXT_SVINVAL), __RISCV_ISA_EXT_DATA(svpbmt, RISCV_ISA_EXT_SVPBMT), - __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM), - __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), __RISCV_ISA_EXT_DATA("", RISCV_ISA_EXT_MAX), }; diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index 694267d1fe81..d3df72c4b94f 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -199,12 +199,12 @@ void __init riscv_fill_hwcap(void) this_hwcap |= isa2hwcap[(unsigned char)(*ext)]; set_bit(*ext - 'a', this_isa); } else { - SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); - SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM); SET_ISA_EXT_MAP("zihintpause", RISCV_ISA_EXT_ZIHINTPAUSE); + SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF); SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC); SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL); + SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT); } #undef SET_ISA_EXT_MAP } -- 2.38.1