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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id w22-20020a9d77d6000000b0066c495a651dsm1350898otl.38.2022.11.30.13.15.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 30 Nov 2022 13:15:37 -0800 (PST) Received: (nullmailer pid 2940448 invoked by uid 1000); Wed, 30 Nov 2022 21:15:37 -0000 Date: Wed, 30 Nov 2022 15:15:37 -0600 From: Rob Herring To: Christoph Niedermaier Cc: linux-serial@vger.kernel.org, linux-arm-kernel@lists.infradead.org, krzysztof.kozlowski+dt@linaro.org, marex@denx.de, jirislaby@kernel.org, Greg Kroah-Hartman , Alexander Dahl , kernel@dh-electronics.com, devicetree@vger.kernel.org Subject: Re: [PATCH V2 1/4] dt_bindings: rs485: Add binding for GPIO that controls Rx enable during Tx Message-ID: <20221130211537.GA2926121-robh@kernel.org> References: <20221123123004.7216-1-cniedermaier@dh-electronics.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20221123123004.7216-1-cniedermaier@dh-electronics.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Nov 23, 2022 at 01:30:01PM +0100, Christoph Niedermaier wrote: > This patch adds a binding for a generic definition of an output GPIO that > indicates the state of rs485-rx-during-tx. The idea is that the hardware > already controls the option receiving during sending before it gets to the > signal receiving hardware. The standard RS485 is a half-duplex bus that in > most cases is driven by an UART controller. The advantage of using this > GPIO is that it is independent of the capabilities of the UART core and > the UART driver. On the hardware side the interface to the bus is > controlled by a transceiver, that has a pin called RE (RX enable) or > similar, which connects the bus to the RX signal of the UART controller. > The GPIO can switch between two states to control the RE pin via an > electrical circuit: > - Active: > The RE pin is always active. The UART RX see everything on the bus and > therefore also what happens with the TX signal on the bus. > - Inactive: > The RE pin is always active, but during sending on the bus the pin RE is > inactive. So basically the receiving during sending is suppressed. > > A possible circuit diagram could look like this: > ┌──────────────────┐ > │ RS485 │ > TX ───────────────┤D │ > │ Transceiver │ > RTS ────┬──────────┤DE │ > │ │ │ > │ ┌─────┐ │ │ > └─┤& │ │ │ > │ ├──┤!RE │ > !rx_during_tx_gpio ──────┤ │ │ │ > └─────┘ │ │ > │ │ > RX ───────────────┤R │ > │ │ > └──────────────────┘ > > Here the RTS pin of the UART core is used to control TX via the transceiver > pin DE (Drive Enable). RE and rx_during_tx_gpio are active low. > > Signed-off-by: Christoph Niedermaier > --- > Cc: Greg Kroah-Hartman > Cc: Rob Herring > Cc: Krzysztof Kozlowski > Cc: Alexander Dahl > Cc: Marek Vasut > Cc: kernel@dh-electronics.com > Cc: devicetree@vger.kernel.org > To: linux-serial@vger.kernel.org > To: linux-arm-kernel@lists.infradead.org > --- > V2: - Rework of the commit message > - Rework GPIO property comment > --- > Documentation/devicetree/bindings/serial/rs485.yaml | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/Documentation/devicetree/bindings/serial/rs485.yaml b/Documentation/devicetree/bindings/serial/rs485.yaml > index 90a1bab40f05..6d780911e342 100644 > --- a/Documentation/devicetree/bindings/serial/rs485.yaml > +++ b/Documentation/devicetree/bindings/serial/rs485.yaml > @@ -51,6 +51,10 @@ properties: > description: GPIO pin to enable RS485 bus termination. > maxItems: 1 > > + rs485-rx-during-tx-gpios: > + description: Output GPIO pin that indicates the state of rs485-rx-during-tx. An output sets the state. An input samples or indicates the state. This should include something about the active state: The active state enables RX during TX. > + maxItems: 1 > + > additionalProperties: true > > ... > -- > 2.11.0 > >