From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents
Date: Mon, 26 Dec 2022 06:21:43 +0200 [thread overview]
Message-ID: <20221226042154.2666748-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org>
On the QCS404 platform the driver for the Global Clock Controller
doens't define gpll0_out_aux and gpll4_out_aux clocks, so it's not
possible to use them as parents. Remove entries for these clocks.
Note: backporting this patch to earlier kernels would also require a
previous patch which switches the gcc driver to use ARRAY_SIZE for
parent data arrays.
Fixes: 652f1813c113 ("clk: qcom: gcc: Add global clock controller driver for QCS404")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 16 ----------------
1 file changed, 16 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index f60a0ab42da1..507c42d7f753 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -25,11 +25,9 @@ enum {
P_CORE_BI_PLL_TEST_SE,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
- P_GPLL0_OUT_AUX,
P_GPLL0_OUT_MAIN,
P_GPLL1_OUT_MAIN,
P_GPLL3_OUT_MAIN,
- P_GPLL4_OUT_AUX,
P_GPLL4_OUT_MAIN,
P_GPLL6_OUT_AUX,
P_HDMI_PHY_PLL_CLK,
@@ -109,28 +107,24 @@ static const char * const gcc_parent_names_4[] = {
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_5[] = {
"cxo",
"dsi0pll_byteclk_src",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
- { P_GPLL0_OUT_AUX, 3 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_6[] = {
"cxo",
"dsi0_phy_pll_out_byteclk",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
@@ -139,7 +133,6 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL3_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_GPLL4_OUT_AUX, 4 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
@@ -148,7 +141,6 @@ static const char * const gcc_parent_names_7[] = {
"gpll0_out_main",
"gpll3_out_main",
"gpll6_out_aux",
- "gpll4_out_aux",
"core_bi_pll_test_se",
};
@@ -207,14 +199,12 @@ static const char * const gcc_parent_names_11[] = {
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_12[] = {
"cxo",
"dsi0pll_pclk_src",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
@@ -237,40 +227,34 @@ static const char * const gcc_parent_names_13[] = {
static const struct parent_map gcc_parent_map_14[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL4_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_14[] = {
"cxo",
"gpll0_out_main",
- "gpll4_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_15[] = {
"cxo",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_GPLL0_OUT_AUX, 2 },
{ P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_16[] = {
"cxo",
"gpll0_out_main",
- "gpll0_out_aux",
"core_bi_pll_test_se",
};
--
2.35.1
next prev parent reply other threads:[~2022-12-26 4:22 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-26 4:21 ` Dmitry Baryshkov [this message]
2022-12-26 4:21 ` [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the " Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Dmitry Baryshkov
2022-12-27 11:33 ` Konrad Dybcio
2022-12-27 18:04 ` (subset) [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Bjorn Andersson
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