From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, Stephen Boyd <swboyd@chromium.org>
Subject: [PATCH v2 08/16] clk: qcom: gcc-qcs404: get rid of the test clock
Date: Mon, 26 Dec 2022 06:21:46 +0200 [thread overview]
Message-ID: <20221226042154.2666748-9-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20221226042154.2666748-1-dmitry.baryshkov@linaro.org>
The test clock isn't in the bindings and apparently it's not used by
anyone upstream. Remove it.
Suggested-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-qcs404.c | 34 ----------------------------------
1 file changed, 34 deletions(-)
diff --git a/drivers/clk/qcom/gcc-qcs404.c b/drivers/clk/qcom/gcc-qcs404.c
index 241768da2263..e1d1d3a700f7 100644
--- a/drivers/clk/qcom/gcc-qcs404.c
+++ b/drivers/clk/qcom/gcc-qcs404.c
@@ -22,7 +22,6 @@
#include "reset.h"
enum {
- P_CORE_BI_PLL_TEST_SE,
P_DSI0_PHY_PLL_OUT_BYTECLK,
P_DSI0_PHY_PLL_OUT_DSICLK,
P_GPLL0_OUT_MAIN,
@@ -39,29 +38,24 @@ enum {
static const struct parent_map gcc_parent_map_0[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_0[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static const char * const gcc_parent_names_ao_0[] = {
"cxo",
"gpll0_ao_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_1[] = {
{ P_XO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_1[] = {
"cxo",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_2[] = {
@@ -82,50 +76,42 @@ static const struct parent_map gcc_parent_map_3[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL6_OUT_AUX, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_3[] = {
"cxo",
"gpll0_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_4[] = {
{ P_XO, 0 },
{ P_GPLL1_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_4[] = {
"cxo",
"gpll1_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_5[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_5[] = {
"cxo",
"dsi0pllbyte",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_6[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_BYTECLK, 2 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_6[] = {
"cxo",
"dsi0pllbyte",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_7[] = {
@@ -133,7 +119,6 @@ static const struct parent_map gcc_parent_map_7[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL3_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_7[] = {
@@ -141,19 +126,16 @@ static const char * const gcc_parent_names_7[] = {
"gpll0_out_main",
"gpll3_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_8[] = {
{ P_XO, 0 },
{ P_HDMI_PHY_PLL_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_8[] = {
"cxo",
"hdmi_pll",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_9[] = {
@@ -161,7 +143,6 @@ static const struct parent_map gcc_parent_map_9[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_9[] = {
@@ -169,43 +150,36 @@ static const char * const gcc_parent_names_9[] = {
"gpll0_out_main",
"dsi0pll",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_10[] = {
{ P_XO, 0 },
{ P_SLEEP_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_10[] = {
"cxo",
"sleep_clk",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_11[] = {
{ P_XO, 0 },
{ P_PCIE_0_PIPE_CLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_11[] = {
"cxo",
"pcie_0_pipe_clk",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_12[] = {
{ P_XO, 0 },
{ P_DSI0_PHY_PLL_OUT_DSICLK, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_12[] = {
"cxo",
"dsi0pll",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_13[] = {
@@ -213,7 +187,6 @@ static const struct parent_map gcc_parent_map_13[] = {
{ P_GPLL0_OUT_MAIN, 1 },
{ P_GPLL4_OUT_MAIN, 2 },
{ P_GPLL6_OUT_AUX, 3 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_13[] = {
@@ -221,41 +194,34 @@ static const char * const gcc_parent_names_13[] = {
"gpll0_out_main",
"gpll4_out_main",
"gpll6_out_aux",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_14[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_14[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_15[] = {
{ P_XO, 0 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_15[] = {
"cxo",
- "core_bi_pll_test_se",
};
static const struct parent_map gcc_parent_map_16[] = {
{ P_XO, 0 },
{ P_GPLL0_OUT_MAIN, 1 },
- { P_CORE_BI_PLL_TEST_SE, 7 },
};
static const char * const gcc_parent_names_16[] = {
"cxo",
"gpll0_out_main",
- "core_bi_pll_test_se",
};
static struct clk_fixed_factor cxo = {
--
2.35.1
next prev parent reply other threads:[~2022-12-26 4:22 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-26 4:21 [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 01/16] dt-bindings: clock: qcom: gcc-qcs404: add two GDSC entries Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 02/16] dt-bindings: clock: qcom: gcc-qcs404: switch to gcc.yaml Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 03/16] dt-bindings: clock: qcom: gcc-qcs404: define clocks/clock-names for QCS404 Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 04/16] clk: qcom: gcc-qcs404: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 05/16] clk: qcom: gcc-qcs404: disable gpll[04]_out_aux parents Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 06/16] clk: qcom: gcc-qcs404: fix names of the DSI clocks used as parents Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 07/16] clk: qcom: gcc-qcs404: fix the name of the HDMI PLL clock Dmitry Baryshkov
2022-12-26 4:21 ` Dmitry Baryshkov [this message]
2022-12-26 4:21 ` [PATCH v2 09/16] clk: qcom: gcc-qcs404: move PLL clocks up Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 10/16] clk: qcom: gcc-qcs404: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 11/16] clk: qcom: gcc-qcs404: sort out the cxo clock Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 12/16] clk: qcom: gcc-qcs404: add support for GDSCs Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 13/16] arm64: dts: qcom: qcs404: use symbol names for PCIe resets Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 14/16] arm64: dts: qcom: qcs404: add power-domains-cells to gcc node Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 15/16] arm64: dts: qcom: qcs404: add clocks to the " Dmitry Baryshkov
2022-12-26 4:21 ` [PATCH v2 16/16] arm64: dts: qcom: qcs404: add xo clock to rpm clock controller Dmitry Baryshkov
2022-12-27 11:33 ` Konrad Dybcio
2022-12-27 18:04 ` (subset) [PATCH v2 00/16] clk: qcom: gcc-qcs404: convert to parent_data Bjorn Andersson
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