From: Andre Przywara <andre.przywara@arm.com>
To: Samuel Holland <samuel@sholland.org>
Cc: Chen-Yu Tsai <wens@csie.org>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
Jisheng Zhang <jszhang@kernel.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor@kernel.org>,
linux-kernel@vger.kernel.org, Heiko Stuebner <heiko@sntech.de>,
Palmer Dabbelt <palmer@rivosinc.com>,
Conor Dooley <conor.dooley@microchip.com>,
Heiko Stuebner <heiko.stuebner@vrull.eu>
Subject: Re: [PATCH v4 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree
Date: Tue, 3 Jan 2023 11:06:13 +0000 [thread overview]
Message-ID: <20230103110613.725f6fa4@donnerap.cambridge.arm.com> (raw)
In-Reply-To: <20221231233851.24923-5-samuel@sholland.org>
On Sat, 31 Dec 2022 17:38:43 -0600
Samuel Holland <samuel@sholland.org> wrote:
Hi,
> D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based
> on a single die, or at a pair of dies derived from the same design.
>
> D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and
> T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of
> the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP
> variants.
>
> Because the original design supported both ARM and RISC-V CPUs, some
> peripherals are duplicated. In addition, all variants except D1s contain
> a HiFi 4 DSP with its own set of peripherals.
>
> The devicetrees are organized to minimize duplication:
> - Common perhiperals are described in sunxi-d1s-t113.dtsi
> - DSP-related peripherals are described in sunxi-d1-t113.dtsi
> - RISC-V specific hardware is described in sun20i-d1s.dtsi
> - Functionality unique to the D1 variant is described in sun20i-d1.dtsi
>
> The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells
> values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC.
I compared to the v2 post (which I already checked against the T113-s
manual) and did not find any extra changes apart from those mentioned in
the changelog below. As my two questions from v2 are answered:
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Many thanks,
Andre
>
> Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Tested-by: Heiko Stuebner <heiko.stuebner@vrull.eu>
> Signed-off-by: Samuel Holland <samuel@sholland.org>
> ---
>
> (no changes since v3)
>
> Changes in v3:
> - Drop dummy DCXO clock-frequency property
> - Decrease the PLIC's riscv,ndev property to 175
> - Fix `make W=1 dtbs` warnings (unnecessary #address/#size-cells)
>
> Changes in v2:
> - Split into separate files for sharing with D1s/R528/T113
> - Use SOC_PERIPHERAL_IRQ macro for interrupts
> - Rename osc24M to dcxo and move the frequency to the board DTs
> - Drop analog LDOs due to the missing binding
> - Correct tcon_top DSI clock reference
> - Add DMIC, DSI controller, and DPHY (bindings are in linux-next)
> - Add CPU OPP table
>
> arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++
> arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++
> .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 +
> .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 837 ++++++++++++++++++
> 4 files changed, 994 insertions(+)
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi
> create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
>
...
next prev parent reply other threads:[~2023-01-03 11:06 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-31 23:38 [PATCH v4 00/12] riscv: Allwinner D1/D1s platform support Samuel Holland
2022-12-31 23:38 ` [PATCH v4 01/12] MAINTAINERS: Match the sun20i family of Allwinner SoCs Samuel Holland
2022-12-31 23:38 ` [PATCH v4 02/12] dt-bindings: vendor-prefixes: Add Allwinner D1/D1s board vendors Samuel Holland
2022-12-31 23:38 ` [PATCH v4 03/12] dt-bindings: riscv: Add Allwinner D1/D1s board compatibles Samuel Holland
2022-12-31 23:38 ` [PATCH v4 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Samuel Holland
2023-01-03 11:06 ` Andre Przywara [this message]
2022-12-31 23:38 ` [PATCH v4 05/12] riscv: dts: allwinner: Add MangoPi MQ devicetree Samuel Holland
2022-12-31 23:38 ` [PATCH v4 06/12] riscv: dts: allwinner: Add Allwinner D1 Nezha devicetree Samuel Holland
2022-12-31 23:38 ` [PATCH v4 07/12] riscv: dts: allwinner: Add Sipeed Lichee RV devicetrees Samuel Holland
2023-01-05 13:55 ` Paul Kocialkowski
2023-01-08 18:42 ` Samuel Holland
2023-01-10 15:58 ` Paul Kocialkowski
2022-12-31 23:38 ` [PATCH v4 08/12] riscv: dts: allwinner: Add MangoPi MQ Pro devicetree Samuel Holland
2022-12-31 23:38 ` [PATCH v4 09/12] riscv: dts: allwinner: Add Dongshan Nezha STU devicetree Samuel Holland
2022-12-31 23:38 ` [PATCH v4 10/12] riscv: dts: allwinner: Add ClockworkPi and DevTerm devicetrees Samuel Holland
2024-06-30 15:09 ` (subset) " Chen-Yu Tsai
2022-12-31 23:38 ` [PATCH v4 11/12] riscv: Add the Allwinner SoC family Kconfig option Samuel Holland
2022-12-31 23:38 ` [PATCH v4 12/12] riscv: defconfig: Enable the Allwinner D1 platform and drivers Samuel Holland
2024-06-30 15:09 ` (subset) [PATCH v4 00/12] riscv: Allwinner D1/D1s platform support Chen-Yu Tsai
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