From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1DBD6C3DA7D for ; Tue, 3 Jan 2023 11:06:24 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233293AbjACLGX (ORCPT ); Tue, 3 Jan 2023 06:06:23 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48414 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S237492AbjACLGT (ORCPT ); Tue, 3 Jan 2023 06:06:19 -0500 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id ECF78E83; Tue, 3 Jan 2023 03:06:17 -0800 (PST) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 532541516; Tue, 3 Jan 2023 03:06:59 -0800 (PST) Received: from donnerap.cambridge.arm.com (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 8D7763F663; Tue, 3 Jan 2023 03:06:15 -0800 (PST) Date: Tue, 3 Jan 2023 11:06:13 +0000 From: Andre Przywara To: Samuel Holland Cc: Chen-Yu Tsai , Jernej Skrabec , linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org, Rob Herring , Jisheng Zhang , linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org, Palmer Dabbelt , Krzysztof Kozlowski , Conor Dooley , linux-kernel@vger.kernel.org, Heiko Stuebner , Palmer Dabbelt , Conor Dooley , Heiko Stuebner Subject: Re: [PATCH v4 04/12] riscv: dts: allwinner: Add the D1/D1s SoC devicetree Message-ID: <20230103110613.725f6fa4@donnerap.cambridge.arm.com> In-Reply-To: <20221231233851.24923-5-samuel@sholland.org> References: <20221231233851.24923-1-samuel@sholland.org> <20221231233851.24923-5-samuel@sholland.org> Organization: ARM X-Mailer: Claws Mail 3.18.0 (GTK+ 2.24.32; aarch64-unknown-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Sat, 31 Dec 2022 17:38:43 -0600 Samuel Holland wrote: Hi, > D1 (aka D1-H), D1s (aka F133), R528, and T113 are a family of SoCs based > on a single die, or at a pair of dies derived from the same design. > > D1 and D1s contain a single T-HEAD Xuantie C906 CPU, whereas R528 and > T113 contain a pair of Cortex-A7's. D1 and R528 are the full version of > the chip with a BGA package, whereas D1s and T113 are low-pin-count QFP > variants. > > Because the original design supported both ARM and RISC-V CPUs, some > peripherals are duplicated. In addition, all variants except D1s contain > a HiFi 4 DSP with its own set of peripherals. > > The devicetrees are organized to minimize duplication: > - Common perhiperals are described in sunxi-d1s-t113.dtsi > - DSP-related peripherals are described in sunxi-d1-t113.dtsi > - RISC-V specific hardware is described in sun20i-d1s.dtsi > - Functionality unique to the D1 variant is described in sun20i-d1.dtsi > > The SOC_PERIPHERAL_IRQ macro handles the different #interrupt-cells > values between the ARM (GIC) and RISC-V (PLIC) versions of the SoC. I compared to the v2 post (which I already checked against the T113-s manual) and did not find any extra changes apart from those mentioned in the changelog below. As my two questions from v2 are answered: Reviewed-by: Andre Przywara Many thanks, Andre > > Acked-by: Jernej Skrabec > Acked-by: Palmer Dabbelt > Reviewed-by: Conor Dooley > Reviewed-by: Heiko Stuebner > Tested-by: Heiko Stuebner > Signed-off-by: Samuel Holland > --- > > (no changes since v3) > > Changes in v3: > - Drop dummy DCXO clock-frequency property > - Decrease the PLIC's riscv,ndev property to 175 > - Fix `make W=1 dtbs` warnings (unnecessary #address/#size-cells) > > Changes in v2: > - Split into separate files for sharing with D1s/R528/T113 > - Use SOC_PERIPHERAL_IRQ macro for interrupts > - Rename osc24M to dcxo and move the frequency to the board DTs > - Drop analog LDOs due to the missing binding > - Correct tcon_top DSI clock reference > - Add DMIC, DSI controller, and DPHY (bindings are in linux-next) > - Add CPU OPP table > > arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi | 66 ++ > arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi | 76 ++ > .../boot/dts/allwinner/sunxi-d1-t113.dtsi | 15 + > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 837 ++++++++++++++++++ > 4 files changed, 994 insertions(+) > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sun20i-d1s.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1-t113.dtsi > create mode 100644 arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > ...