* [PATCH 0/3] arm64: dts: qcom: sm8550-mtp: enable DSI panel
@ 2023-01-04 9:18 Neil Armstrong
2023-01-04 9:18 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices Neil Armstrong
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Neil Armstrong @ 2023-01-04 9:18 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring,
Krzysztof Kozlowski
Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong
Add device tree nodes for MDSS, DPU and DSI devices on Qualcomm SM8550
platform. Enable these devices and add the DSI panel on the MTP device.
Dependencies:
- [1] SM8550 base DT
- [2] MDSS/DPU/DSI bindings
- [3] DISPCC bindings
- [4] VTDR6130 Panel bindings
[1] https://lore.kernel.org/all/20221230202230.2493494-1-abel.vesa@linaro.org/
[2] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-mdss-dsi-v1-0-9ccd7e652fcd@linaro.org/
[3] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-dispcc-v1-0-81bfcc26b2dc@linaro.org/
[4] https://lore.kernel.org/all/20230103-topic-sm8550-upstream-vtdr6130-panel-v1-0-9b746b858378@linaro.org/
To: Andy Gross <agross@kernel.org>
To: Bjorn Andersson <andersson@kernel.org>
To: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Rob Herring <robh+dt@kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
---
Neil Armstrong (3):
arm64: dts: qcom: sm8550: add display hardware devices
arm64: dts: qcom: sm8550-mtp: enable display hardware
arm64: dts: qcom: sm8550-mtp: add DSI panel
arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 78 +++++++++
arch/arm64/boot/dts/qcom/sm8550.dtsi | 295 ++++++++++++++++++++++++++++++++
2 files changed, 373 insertions(+)
---
base-commit: 3413711161cca59e1247d3c5ba0c6261d2b20dc6
change-id: 20230104-topic-sm8550-upstream-dts-display-aa22b568ea17
Best regards,
--
Neil Armstrong <neil.armstrong@linaro.org>
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices 2023-01-04 9:18 [PATCH 0/3] arm64: dts: qcom: sm8550-mtp: enable DSI panel Neil Armstrong @ 2023-01-04 9:18 ` Neil Armstrong 2023-01-04 10:24 ` Konrad Dybcio 2023-01-04 9:18 ` [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware Neil Armstrong 2023-01-04 9:18 ` [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel Neil Armstrong 2 siblings, 1 reply; 7+ messages in thread From: Neil Armstrong @ 2023-01-04 9:18 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add devices tree nodes describing display hardware on SM8550: - Display Clock Controller - MDSS - MDP - two DSI controllers and DSI PHYs This does not provide support for DP controllers present on the SM8550. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550.dtsi | 295 +++++++++++++++++++++++++++++++++++ 1 file changed, 295 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi index f1760eea3d6b..3b68bba81473 100644 --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi @@ -1425,6 +1425,301 @@ opp-202000000 { }; }; + mdss: mdss@ae00000 { + compatible = "qcom,sm8550-mdss"; + reg = <0 0x0ae00000 0 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; + interconnect-names = "mdp0-mem", "mdp1-mem"; + + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x1c00 0x2>; + + #address-cells = <2>; + #size-cells = <2>; + ranges; + + status = "disabled"; + + mdss_mdp: display-controller@ae01000 { + compatible = "qcom,sm8550-dpu"; + reg = <0 0x0ae01000 0 0x8f000>, + <0 0x0aeb0000 0 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&gcc GCC_DISP_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + clock-names = "bus", + "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&mdss_dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-325000000 { + opp-hz = /bits/ 64 <325000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-375000000 { + opp-hz = /bits/ 64 <375000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-514000000 { + opp-hz = /bits/ 64 <514000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + mdss_dsi0: dsi@ae94000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae94000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + phys = <&mdss_dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi0_out: endpoint { + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible = "qcom,dsi-phy-4nm-8550"; + reg = <0 0x0ae95000 0 0x200>, + <0 0x0ae95200 0 0x280>, + <0 0x0ae95500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + + mdss_dsi1: dsi@ae96000 { + compatible = "qcom,mdss-dsi-ctrl"; + reg = <0 0x0ae96000 0 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; + + operating-points-v2 = <&mdss_dsi_opp_table>; + power-domains = <&rpmhpd SM8550_MMCX>; + + phys = <&mdss_dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + mdss_dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible = "qcom,dsi-phy-4nm-8550"; + reg = <0 0x0ae97000 0 0x200>, + <0 0x0ae97200 0 0x280>, + <0 0x0ae97500 0 0x400>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + + status = "disabled"; + }; + }; + + dispcc: clock-controller@af00000 { + compatible = "qcom,sm8550-dispcc"; + reg = <0 0x0af00000 0 0x20000>; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&rpmhcc RPMH_CXO_CLK_A>, + <&gcc GCC_DISP_AHB_CLK>, + <&sleep_clk>, + <&mdss_dsi0_phy 0>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi1_phy 0>, + <&mdss_dsi1_phy 1>, + <0>, /* dp0 */ + <0>, + <0>, /* dp1 */ + <0>, + <0>, /* dp2 */ + <0>, + <0>, /* dp3 */ + <0>; + power-domains = <&rpmhpd SM8550_MMCX>; + required-opps = <&rpmhpd_opp_low_svs>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + status = "disabled"; + }; + pdc: interrupt-controller@b220000 { compatible = "qcom,sm8550-pdc", "qcom,pdc"; reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices 2023-01-04 9:18 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices Neil Armstrong @ 2023-01-04 10:24 ` Konrad Dybcio 2023-01-04 10:42 ` Neil Armstrong 0 siblings, 1 reply; 7+ messages in thread From: Konrad Dybcio @ 2023-01-04 10:24 UTC (permalink / raw) To: Neil Armstrong, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 4.01.2023 10:18, Neil Armstrong wrote: > Add devices tree nodes describing display hardware on SM8550: > - Display Clock Controller > - MDSS > - MDP > - two DSI controllers and DSI PHYs > > This does not provide support for DP controllers present on the SM8550. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > arch/arm64/boot/dts/qcom/sm8550.dtsi | 295 +++++++++++++++++++++++++++++++++++ > 1 file changed, 295 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi > index f1760eea3d6b..3b68bba81473 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi > @@ -1425,6 +1425,301 @@ opp-202000000 { > }; > }; > > + mdss: mdss@ae00000 { display-subsystem@ > + compatible = "qcom,sm8550-mdss"; > + reg = <0 0x0ae00000 0 0x1000>; We settled on 0x0 being prefered instead of decimal zero for reg, though I think I personally asked Abel to make it '0' in 8550 a few months ago.. Thoughts, Krzysztof, Bjorn? > + reg-names = "mdss"; > + > + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, > + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; > + interconnect-names = "mdp0-mem", "mdp1-mem"; > + > + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; > + > + power-domains = <&dispcc MDSS_GDSC>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>; > + > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-controller; > + #interrupt-cells = <1>; > + > + iommus = <&apps_smmu 0x1c00 0x2>; > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; We recently started an endless quest to try and regulate the property order [1], please shuffle these around: compat reg reg-names interrupt* clocks clock-names resets reset-names power-domains interconnects interconnect-names The rest (iommus #-cells, ranges) we still haven't quite agreed on, so I guess they may stay where they are.. Please do the same for other nodes. Otherwise this looks good! Konrad [1] https://github.com/konradybcio-work/dt_review/blob/master/README.md > + > + status = "disabled"; > + > + mdss_mdp: display-controller@ae01000 { > + compatible = "qcom,sm8550-dpu"; > + reg = <0 0x0ae01000 0 0x8f000>, > + <0 0x0aeb0000 0 0x2008>; > + reg-names = "mdp", "vbif"; > + > + clocks = <&gcc GCC_DISP_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, > + <&dispcc DISP_CC_MDSS_MDP_CLK>, > + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + clock-names = "bus", > + "nrt_bus", > + "iface", > + "lut", > + "core", > + "vsync"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&mdp_opp_table>; > + power-domains = <&rpmhpd SM8550_MMCX>; > + > + interrupt-parent = <&mdss>; > + interrupts = <0>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dpu_intf1_out: endpoint { > + remote-endpoint = <&mdss_dsi0_in>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + dpu_intf2_out: endpoint { > + remote-endpoint = <&mdss_dsi1_in>; > + }; > + }; > + }; > + > + mdp_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-200000000 { > + opp-hz = /bits/ 64 <200000000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-325000000 { > + opp-hz = /bits/ 64 <325000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-375000000 { > + opp-hz = /bits/ 64 <375000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + > + opp-514000000 { > + opp-hz = /bits/ 64 <514000000>; > + required-opps = <&rpmhpd_opp_nom>; > + }; > + }; > + }; > + > + mdss_dsi0: dsi@ae94000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae94000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <4>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, > + <&dispcc DISP_CC_MDSS_ESC0_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; > + > + operating-points-v2 = <&mdss_dsi_opp_table>; > + power-domains = <&rpmhpd SM8550_MMCX>; > + > + phys = <&mdss_dsi0_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dsi0_in: endpoint { > + remote-endpoint = <&dpu_intf1_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dsi0_out: endpoint { > + }; > + }; > + }; > + > + mdss_dsi_opp_table: opp-table { > + compatible = "operating-points-v2"; > + > + opp-187500000 { > + opp-hz = /bits/ 64 <187500000>; > + required-opps = <&rpmhpd_opp_low_svs>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&rpmhpd_opp_svs>; > + }; > + > + opp-358000000 { > + opp-hz = /bits/ 64 <358000000>; > + required-opps = <&rpmhpd_opp_svs_l1>; > + }; > + }; > + }; > + > + mdss_dsi0_phy: phy@ae95000 { > + compatible = "qcom,dsi-phy-4nm-8550"; > + reg = <0 0x0ae95000 0 0x200>, > + <0 0x0ae95200 0 0x280>, > + <0 0x0ae95500 0 0x400>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + > + mdss_dsi1: dsi@ae96000 { > + compatible = "qcom,mdss-dsi-ctrl"; > + reg = <0 0x0ae96000 0 0x400>; > + reg-names = "dsi_ctrl"; > + > + interrupt-parent = <&mdss>; > + interrupts = <5>; > + > + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, > + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, > + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, > + <&dispcc DISP_CC_MDSS_ESC1_CLK>, > + <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&gcc GCC_DISP_HF_AXI_CLK>; > + clock-names = "byte", > + "byte_intf", > + "pixel", > + "core", > + "iface", > + "bus"; > + > + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; > + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; > + > + operating-points-v2 = <&mdss_dsi_opp_table>; > + power-domains = <&rpmhpd SM8550_MMCX>; > + > + phys = <&mdss_dsi1_phy>; > + phy-names = "dsi"; > + > + #address-cells = <1>; > + #size-cells = <0>; > + > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + mdss_dsi1_in: endpoint { > + remote-endpoint = <&dpu_intf2_out>; > + }; > + }; > + > + port@1 { > + reg = <1>; > + mdss_dsi1_out: endpoint { > + }; > + }; > + }; > + }; > + > + mdss_dsi1_phy: phy@ae97000 { > + compatible = "qcom,dsi-phy-4nm-8550"; > + reg = <0 0x0ae97000 0 0x200>, > + <0 0x0ae97200 0 0x280>, > + <0 0x0ae97500 0 0x400>; > + reg-names = "dsi_phy", > + "dsi_phy_lane", > + "dsi_pll"; > + > + #clock-cells = <1>; > + #phy-cells = <0>; > + > + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, > + <&rpmhcc RPMH_CXO_CLK>; > + clock-names = "iface", "ref"; > + > + status = "disabled"; > + }; > + }; > + > + dispcc: clock-controller@af00000 { > + compatible = "qcom,sm8550-dispcc"; > + reg = <0 0x0af00000 0 0x20000>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&rpmhcc RPMH_CXO_CLK_A>, > + <&gcc GCC_DISP_AHB_CLK>, > + <&sleep_clk>, > + <&mdss_dsi0_phy 0>, > + <&mdss_dsi0_phy 1>, > + <&mdss_dsi1_phy 0>, > + <&mdss_dsi1_phy 1>, > + <0>, /* dp0 */ > + <0>, > + <0>, /* dp1 */ > + <0>, > + <0>, /* dp2 */ > + <0>, > + <0>, /* dp3 */ > + <0>; > + power-domains = <&rpmhpd SM8550_MMCX>; > + required-opps = <&rpmhpd_opp_low_svs>; > + #clock-cells = <1>; > + #reset-cells = <1>; > + #power-domain-cells = <1>; > + status = "disabled"; > + }; > + > pdc: interrupt-controller@b220000 { > compatible = "qcom,sm8550-pdc", "qcom,pdc"; > reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; > ^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices 2023-01-04 10:24 ` Konrad Dybcio @ 2023-01-04 10:42 ` Neil Armstrong 0 siblings, 0 replies; 7+ messages in thread From: Neil Armstrong @ 2023-01-04 10:42 UTC (permalink / raw) To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 04/01/2023 11:24, Konrad Dybcio wrote: > > > On 4.01.2023 10:18, Neil Armstrong wrote: >> Add devices tree nodes describing display hardware on SM8550: >> - Display Clock Controller >> - MDSS >> - MDP >> - two DSI controllers and DSI PHYs >> >> This does not provide support for DP controllers present on the SM8550. >> >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> arch/arm64/boot/dts/qcom/sm8550.dtsi | 295 +++++++++++++++++++++++++++++++++++ >> 1 file changed, 295 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi >> index f1760eea3d6b..3b68bba81473 100644 >> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi I just saw I forgot to include the dispcc bindings header, I wonder how it got dropped... >> @@ -1425,6 +1425,301 @@ opp-202000000 { >> }; >> }; >> >> + mdss: mdss@ae00000 { > display-subsystem@ Ack > >> + compatible = "qcom,sm8550-mdss"; >> + reg = <0 0x0ae00000 0 0x1000>; > We settled on 0x0 being prefered instead of decimal zero for reg, > though I think I personally asked Abel to make it '0' in 8550 a few > months ago.. Thoughts, Krzysztof, Bjorn? Indeed, Abel switched the entire sm8550 to 0, I'll update to what's prefered. > >> + reg-names = "mdss"; >> + >> + interconnects = <&mmss_noc MASTER_MDP 0 &gem_noc SLAVE_LLCC 0>, >> + <&mc_virt MASTER_LLCC 0 &mc_virt SLAVE_EBI1 0>; >> + interconnect-names = "mdp0-mem", "mdp1-mem"; >> + >> + resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; >> + >> + power-domains = <&dispcc MDSS_GDSC>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>; >> + >> + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; >> + interrupt-controller; >> + #interrupt-cells = <1>; >> + >> + iommus = <&apps_smmu 0x1c00 0x2>; >> + >> + #address-cells = <2>; >> + #size-cells = <2>; >> + ranges; > We recently started an endless quest to try and regulate the property > order [1], please shuffle these around: > > compat > reg > reg-names > interrupt* > clocks > clock-names > resets > reset-names > power-domains > interconnects > interconnect-names Ack > > The rest (iommus #-cells, ranges) we still haven't quite agreed > on, so I guess they may stay where they are.. > > Please do the same for other nodes. Otherwise this looks good! Thanks, Neil > > Konrad > > [1] https://github.com/konradybcio-work/dt_review/blob/master/README.md I was looking for this, I forgot were you shared it, thanks :-) >> + >> + status = "disabled"; >> + >> + mdss_mdp: display-controller@ae01000 { >> + compatible = "qcom,sm8550-dpu"; >> + reg = <0 0x0ae01000 0 0x8f000>, >> + <0 0x0aeb0000 0 0x2008>; >> + reg-names = "mdp", "vbif"; >> + >> + clocks = <&gcc GCC_DISP_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, >> + <&dispcc DISP_CC_MDSS_MDP_CLK>, >> + <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + clock-names = "bus", >> + "nrt_bus", >> + "iface", >> + "lut", >> + "core", >> + "vsync"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; >> + assigned-clock-rates = <19200000>; >> + >> + operating-points-v2 = <&mdp_opp_table>; >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <0>; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + dpu_intf1_out: endpoint { >> + remote-endpoint = <&mdss_dsi0_in>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + dpu_intf2_out: endpoint { >> + remote-endpoint = <&mdss_dsi1_in>; >> + }; >> + }; >> + }; >> + >> + mdp_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-200000000 { >> + opp-hz = /bits/ 64 <200000000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-325000000 { >> + opp-hz = /bits/ 64 <325000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-375000000 { >> + opp-hz = /bits/ 64 <375000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + >> + opp-514000000 { >> + opp-hz = /bits/ 64 <514000000>; >> + required-opps = <&rpmhpd_opp_nom>; >> + }; >> + }; >> + }; >> + >> + mdss_dsi0: dsi@ae94000 { >> + compatible = "qcom,mdss-dsi-ctrl"; >> + reg = <0 0x0ae94000 0 0x400>; >> + reg-names = "dsi_ctrl"; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <4>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, >> + <&dispcc DISP_CC_MDSS_ESC0_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>; >> + clock-names = "byte", >> + "byte_intf", >> + "pixel", >> + "core", >> + "iface", >> + "bus"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; >> + assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>; >> + >> + operating-points-v2 = <&mdss_dsi_opp_table>; >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + >> + phys = <&mdss_dsi0_phy>; >> + phy-names = "dsi"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + mdss_dsi0_in: endpoint { >> + remote-endpoint = <&dpu_intf1_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + mdss_dsi0_out: endpoint { >> + }; >> + }; >> + }; >> + >> + mdss_dsi_opp_table: opp-table { >> + compatible = "operating-points-v2"; >> + >> + opp-187500000 { >> + opp-hz = /bits/ 64 <187500000>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + }; >> + >> + opp-300000000 { >> + opp-hz = /bits/ 64 <300000000>; >> + required-opps = <&rpmhpd_opp_svs>; >> + }; >> + >> + opp-358000000 { >> + opp-hz = /bits/ 64 <358000000>; >> + required-opps = <&rpmhpd_opp_svs_l1>; >> + }; >> + }; >> + }; >> + >> + mdss_dsi0_phy: phy@ae95000 { >> + compatible = "qcom,dsi-phy-4nm-8550"; >> + reg = <0 0x0ae95000 0 0x200>, >> + <0 0x0ae95200 0 0x280>, >> + <0 0x0ae95500 0 0x400>; >> + reg-names = "dsi_phy", >> + "dsi_phy_lane", >> + "dsi_pll"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", "ref"; >> + >> + status = "disabled"; >> + }; >> + >> + mdss_dsi1: dsi@ae96000 { >> + compatible = "qcom,mdss-dsi-ctrl"; >> + reg = <0 0x0ae96000 0 0x400>; >> + reg-names = "dsi_ctrl"; >> + >> + interrupt-parent = <&mdss>; >> + interrupts = <5>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, >> + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, >> + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, >> + <&dispcc DISP_CC_MDSS_ESC1_CLK>, >> + <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&gcc GCC_DISP_HF_AXI_CLK>; >> + clock-names = "byte", >> + "byte_intf", >> + "pixel", >> + "core", >> + "iface", >> + "bus"; >> + >> + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; >> + assigned-clock-parents = <&mdss_dsi1_phy 0>, <&mdss_dsi1_phy 1>; >> + >> + operating-points-v2 = <&mdss_dsi_opp_table>; >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + >> + phys = <&mdss_dsi1_phy>; >> + phy-names = "dsi"; >> + >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + status = "disabled"; >> + >> + ports { >> + #address-cells = <1>; >> + #size-cells = <0>; >> + >> + port@0 { >> + reg = <0>; >> + mdss_dsi1_in: endpoint { >> + remote-endpoint = <&dpu_intf2_out>; >> + }; >> + }; >> + >> + port@1 { >> + reg = <1>; >> + mdss_dsi1_out: endpoint { >> + }; >> + }; >> + }; >> + }; >> + >> + mdss_dsi1_phy: phy@ae97000 { >> + compatible = "qcom,dsi-phy-4nm-8550"; >> + reg = <0 0x0ae97000 0 0x200>, >> + <0 0x0ae97200 0 0x280>, >> + <0 0x0ae97500 0 0x400>; >> + reg-names = "dsi_phy", >> + "dsi_phy_lane", >> + "dsi_pll"; >> + >> + #clock-cells = <1>; >> + #phy-cells = <0>; >> + >> + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, >> + <&rpmhcc RPMH_CXO_CLK>; >> + clock-names = "iface", "ref"; >> + >> + status = "disabled"; >> + }; >> + }; >> + >> + dispcc: clock-controller@af00000 { >> + compatible = "qcom,sm8550-dispcc"; >> + reg = <0 0x0af00000 0 0x20000>; >> + clocks = <&rpmhcc RPMH_CXO_CLK>, >> + <&rpmhcc RPMH_CXO_CLK_A>, >> + <&gcc GCC_DISP_AHB_CLK>, >> + <&sleep_clk>, >> + <&mdss_dsi0_phy 0>, >> + <&mdss_dsi0_phy 1>, >> + <&mdss_dsi1_phy 0>, >> + <&mdss_dsi1_phy 1>, >> + <0>, /* dp0 */ >> + <0>, >> + <0>, /* dp1 */ >> + <0>, >> + <0>, /* dp2 */ >> + <0>, >> + <0>, /* dp3 */ >> + <0>; >> + power-domains = <&rpmhpd SM8550_MMCX>; >> + required-opps = <&rpmhpd_opp_low_svs>; >> + #clock-cells = <1>; >> + #reset-cells = <1>; >> + #power-domain-cells = <1>; >> + status = "disabled"; >> + }; >> + >> pdc: interrupt-controller@b220000 { >> compatible = "qcom,sm8550-pdc", "qcom,pdc"; >> reg = <0 0x0b220000 0 0x30000>, <0 0x174000f0 0 0x64>; >> ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware 2023-01-04 9:18 [PATCH 0/3] arm64: dts: qcom: sm8550-mtp: enable DSI panel Neil Armstrong 2023-01-04 9:18 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices Neil Armstrong @ 2023-01-04 9:18 ` Neil Armstrong 2023-01-04 10:25 ` Konrad Dybcio 2023-01-04 9:18 ` [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel Neil Armstrong 2 siblings, 1 reply; 7+ messages in thread From: Neil Armstrong @ 2023-01-04 9:18 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Enable MDSS/DPU/DSI0 on SM8550-MTP device. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 8586e16d6079..5b7e301cc2a2 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -359,6 +359,28 @@ vreg_l3g_1p2: ldo3 { }; }; +&dispcc { + status = "okay"; +}; + +&mdss { + status = "okay"; +}; + +&mdss_dsi0 { + vdda-supply = <&vreg_l3e_1p2>; + status = "okay"; +}; + +&mdss_dsi0_phy { + vdds-supply = <&vreg_l1e_0p88>; + status = "okay"; +}; + +&mdss_mdp { + status = "okay"; +}; + &pm8550_gpios { sdc2_card_det_n: sdc2-card-det-state { pins = "gpio12"; -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware 2023-01-04 9:18 ` [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware Neil Armstrong @ 2023-01-04 10:25 ` Konrad Dybcio 0 siblings, 0 replies; 7+ messages in thread From: Konrad Dybcio @ 2023-01-04 10:25 UTC (permalink / raw) To: Neil Armstrong, Andy Gross, Bjorn Andersson, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel On 4.01.2023 10:18, Neil Armstrong wrote: > Enable MDSS/DPU/DSI0 on SM8550-MTP device. > > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Konrad > arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > index 8586e16d6079..5b7e301cc2a2 100644 > --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts > @@ -359,6 +359,28 @@ vreg_l3g_1p2: ldo3 { > }; > }; > > +&dispcc { > + status = "okay"; > +}; > + > +&mdss { > + status = "okay"; > +}; > + > +&mdss_dsi0 { > + vdda-supply = <&vreg_l3e_1p2>; > + status = "okay"; > +}; > + > +&mdss_dsi0_phy { > + vdds-supply = <&vreg_l1e_0p88>; > + status = "okay"; > +}; > + > +&mdss_mdp { > + status = "okay"; > +}; > + > &pm8550_gpios { > sdc2_card_det_n: sdc2-card-det-state { > pins = "gpio12"; > ^ permalink raw reply [flat|nested] 7+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel 2023-01-04 9:18 [PATCH 0/3] arm64: dts: qcom: sm8550-mtp: enable DSI panel Neil Armstrong 2023-01-04 9:18 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices Neil Armstrong 2023-01-04 9:18 ` [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware Neil Armstrong @ 2023-01-04 9:18 ` Neil Armstrong 2 siblings, 0 replies; 7+ messages in thread From: Neil Armstrong @ 2023-01-04 9:18 UTC (permalink / raw) To: Andy Gross, Bjorn Andersson, Konrad Dybcio, Rob Herring, Krzysztof Kozlowski Cc: linux-arm-msm, devicetree, linux-kernel, Neil Armstrong Add nodes for the Visionox VTDR6130 found on the SM8550-MTP device. TLMM states are also added for the Panel reset GPIO and Tearing Effect signal for when the panel is running in DSI Command mode. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- arch/arm64/boot/dts/qcom/sm8550-mtp.dts | 56 +++++++++++++++++++++++++++++++++ 1 file changed, 56 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts index 5b7e301cc2a2..cbb63a31f0ff 100644 --- a/arch/arm64/boot/dts/qcom/sm8550-mtp.dts +++ b/arch/arm64/boot/dts/qcom/sm8550-mtp.dts @@ -370,6 +370,34 @@ &mdss { &mdss_dsi0 { vdda-supply = <&vreg_l3e_1p2>; status = "okay"; + + panel@0 { + compatible = "visionox,vtdr6130"; + reg = <0>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sde_dsi_active>, <&sde_te_active>; + pinctrl-1 = <&sde_dsi_suspend>, <&sde_te_suspend>; + + vddio-supply = <&vreg_l12b_1p8>; + vci-supply = <&vreg_l13b_3p0>; + vdd-supply = <&vreg_l11b_1p2>; + + reset-gpios = <&tlmm 133 GPIO_ACTIVE_LOW>; + + status = "okay"; + + port { + panel0_in: endpoint { + remote-endpoint = <&mdss_dsi0_out>; + }; + }; + }; +}; + +&mdss_dsi0_out { + remote-endpoint = <&panel0_in>; + data-lanes = <0 1 2 3>; }; &mdss_dsi0_phy { @@ -415,6 +443,34 @@ &sleep_clk { &tlmm { gpio-reserved-ranges = <32 8>; + + sde_dsi_active: sde-dsi-active-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <8>; + bias-disable; + }; + + sde_dsi_suspend: sde-dsi-suspend-state { + pins = "gpio133"; + function = "gpio"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_active: sde-te-active-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; + + sde_te_suspend: sde-te-suspend-state { + pins = "gpio86"; + function = "mdp_vsync"; + drive-strength = <2>; + bias-pull-down; + }; }; &uart7 { -- 2.34.1 ^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-01-04 10:43 UTC | newest] Thread overview: 7+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-01-04 9:18 [PATCH 0/3] arm64: dts: qcom: sm8550-mtp: enable DSI panel Neil Armstrong 2023-01-04 9:18 ` [PATCH 1/3] arm64: dts: qcom: sm8550: add display hardware devices Neil Armstrong 2023-01-04 10:24 ` Konrad Dybcio 2023-01-04 10:42 ` Neil Armstrong 2023-01-04 9:18 ` [PATCH 2/3] arm64: dts: qcom: sm8550-mtp: enable display hardware Neil Armstrong 2023-01-04 10:25 ` Konrad Dybcio 2023-01-04 9:18 ` [PATCH 3/3] arm64: dts: qcom: sm8550-mtp: add DSI panel Neil Armstrong
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