From: Markus Schneider-Pargmann <msp@baylibre.com>
To: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Cc: mturquette@baylibre.com, sboyd@kernel.org,
matthias.bgg@gmail.com, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, wenst@chromium.org,
johnson.wang@mediatek.com, miles.chen@mediatek.com,
fparent@baylibre.com, chun-jie.chen@mediatek.com,
sam.shih@mediatek.com, y.oudjana@protonmail.com,
nfraprado@collabora.com, rex-bc.chen@mediatek.com,
ryder.lee@kernel.org, daniel@makrotopia.org,
jose.exposito89@gmail.com, yangyingliang@huawei.com,
pablo.sun@mediatek.com, weiyi.lu@mediatek.com, ikjn@chromium.org,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
linux-mediatek@lists.infradead.org, devicetree@vger.kernel.org,
kernel@collabora.com
Subject: Re: [PATCH v2 01/23] clk: mediatek: mt8192: Correctly unregister and free clocks on failure
Date: Wed, 4 Jan 2023 11:55:35 +0100 [thread overview]
Message-ID: <20230104105535.j7zasooq5u2xgng6@blmsp> (raw)
In-Reply-To: <20221223094259.87373-2-angelogioacchino.delregno@collabora.com>
Hi Angelo,
On Fri, Dec 23, 2022 at 10:42:37AM +0100, AngeloGioacchino Del Regno wrote:
> If anything fails during probe of the clock controller(s), unregister
> (and kfree!) whatever we have previously registered to leave with a
> clean state and prevent leaks.
>
> Fixes: 710573dee31b ("clk: mediatek: Add MT8192 basic clocks support")
> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> drivers/clk/mediatek/clk-mt8192.c | 72 ++++++++++++++++++++++++-------
> 1 file changed, 56 insertions(+), 16 deletions(-)
>
> diff --git a/drivers/clk/mediatek/clk-mt8192.c b/drivers/clk/mediatek/clk-mt8192.c
> index 0e88588b2c49..eff66ca6c6a7 100644
> --- a/drivers/clk/mediatek/clk-mt8192.c
> +++ b/drivers/clk/mediatek/clk-mt8192.c
> @@ -1100,27 +1100,61 @@ static int clk_mt8192_top_probe(struct platform_device *pdev)
> if (IS_ERR(base))
> return PTR_ERR(base);
>
> - mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
> - mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
> - mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> - mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node, &mt8192_clk_lock,
> - top_clk_data);
> - mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base, &mt8192_clk_lock,
> - top_clk_data);
> - mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base, &mt8192_clk_lock,
> - top_clk_data);
> - r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> + r = mtk_clk_register_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks), top_clk_data);
> if (r)
> return r;
>
> + r = mtk_clk_register_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
> + if (r)
> + goto unregister_fixed_clks;
> +
> + r = mtk_clk_register_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> + if (r)
> + goto unregister_early_factors;
> +
> + r = mtk_clk_register_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), node,
> + &mt8192_clk_lock, top_clk_data);
> + if (r)
> + goto unregister_factors;
> +
> + r = mtk_clk_register_composites(top_muxes, ARRAY_SIZE(top_muxes), base,
> + &mt8192_clk_lock, top_clk_data);
> + if (r)
> + goto unregister_muxes;
> +
> + r = mtk_clk_register_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), base,
> + &mt8192_clk_lock, top_clk_data);
> + if (r)
> + goto unregister_top_composites;
> +
> + r = mtk_clk_register_gates(node, top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> + if (r)
> + goto unregister_adj_divs_composites;
> +
> r = clk_mt8192_reg_mfg_mux_notifier(&pdev->dev,
> top_clk_data->hws[CLK_TOP_MFG_PLL_SEL]->clk);
> if (r)
> - return r;
> -
> + goto unregister_gates;
>
> return of_clk_add_hw_provider(node, of_clk_hw_onecell_get,
> top_clk_data);
I think you may have missed this one. If of_clk_add_hw_provider fails
you should unregister all of the above, right?
Otherwise:
Reviewed-by: Markus Schneider-Pargmann <msp@baylibre.com>
> +
> +unregister_gates:
> + mtk_clk_unregister_gates(top_clks, ARRAY_SIZE(top_clks), top_clk_data);
> +unregister_adj_divs_composites:
> + mtk_clk_unregister_composites(top_adj_divs, ARRAY_SIZE(top_adj_divs), top_clk_data);
> +unregister_top_composites:
> + mtk_clk_unregister_composites(top_muxes, ARRAY_SIZE(top_muxes), top_clk_data);
> +unregister_muxes:
> + mtk_clk_unregister_muxes(top_mtk_muxes, ARRAY_SIZE(top_mtk_muxes), top_clk_data);
> +unregister_factors:
> + mtk_clk_unregister_factors(top_divs, ARRAY_SIZE(top_divs), top_clk_data);
> +unregister_early_factors:
> + mtk_clk_unregister_factors(top_early_divs, ARRAY_SIZE(top_early_divs), top_clk_data);
> +unregister_fixed_clks:
> + mtk_clk_unregister_fixed_clks(top_fixed_clks, ARRAY_SIZE(top_fixed_clks),
> + top_clk_data);
> + return r;
> }
>
> static int clk_mt8192_infra_probe(struct platform_device *pdev)
> @@ -1139,14 +1173,16 @@ static int clk_mt8192_infra_probe(struct platform_device *pdev)
>
> r = mtk_register_reset_controller_with_dev(&pdev->dev, &clk_rst_desc);
> if (r)
> - goto free_clk_data;
> + goto unregister_gates;
>
> r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> if (r)
> - goto free_clk_data;
> + goto unregister_gates;
>
> return r;
>
> +unregister_gates:
> + mtk_clk_unregister_gates(infra_clks, ARRAY_SIZE(infra_clks), clk_data);
> free_clk_data:
> mtk_free_clk_data(clk_data);
> return r;
> @@ -1168,10 +1204,12 @@ static int clk_mt8192_peri_probe(struct platform_device *pdev)
>
> r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> if (r)
> - goto free_clk_data;
> + goto unregister_gates;
>
> return r;
>
> +unregister_gates:
> + mtk_clk_unregister_gates(peri_clks, ARRAY_SIZE(peri_clks), clk_data);
> free_clk_data:
> mtk_free_clk_data(clk_data);
> return r;
> @@ -1194,10 +1232,12 @@ static int clk_mt8192_apmixed_probe(struct platform_device *pdev)
>
> r = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
> if (r)
> - goto free_clk_data;
> + goto unregister_gates;
>
> return r;
>
> +unregister_gates:
> + mtk_clk_unregister_gates(apmixed_clks, ARRAY_SIZE(apmixed_clks), clk_data);
> free_clk_data:
> mtk_free_clk_data(clk_data);
> return r;
> --
> 2.39.0
>
next prev parent reply other threads:[~2023-01-04 10:57 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-12-23 9:42 [PATCH v2 00/23] MediaTek clocks cleanups and improvements AngeloGioacchino Del Regno
2022-12-23 9:42 ` [PATCH v2 01/23] clk: mediatek: mt8192: Correctly unregister and free clocks on failure AngeloGioacchino Del Regno
2022-12-26 6:55 ` Chen-Yu Tsai
2023-01-04 10:55 ` Markus Schneider-Pargmann [this message]
2022-12-23 9:42 ` [PATCH v2 02/23] clk: mediatek: mt8192: Propagate struct device for gate clocks AngeloGioacchino Del Regno
2022-12-26 6:56 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 03/23] clk: mediatek: clk-gate: Propagate struct device with mtk_clk_register_gates() AngeloGioacchino Del Regno
2022-12-26 7:05 ` Chen-Yu Tsai
2023-01-04 11:21 ` Markus Schneider-Pargmann
2023-01-10 11:05 ` AngeloGioacchino Del Regno
2022-12-23 9:42 ` [PATCH v2 04/23] clk: mediatek: cpumux: Propagate struct device where possible AngeloGioacchino Del Regno
2022-12-26 7:07 ` Chen-Yu Tsai
2023-01-06 17:00 ` Markus Schneider-Pargmann
2022-12-23 9:42 ` [PATCH v2 05/23] clk: mediatek: clk-mtk: Propagate struct device for composites AngeloGioacchino Del Regno
2022-12-30 4:37 ` Chen-Yu Tsai
2023-01-06 17:09 ` Markus Schneider-Pargmann
2022-12-23 9:42 ` [PATCH v2 06/23] clk: mediatek: clk-mux: Propagate struct device for mtk-mux AngeloGioacchino Del Regno
2022-12-30 4:43 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 07/23] clk: mediatek: clk-mtk: Add dummy clock ops AngeloGioacchino Del Regno
2022-12-28 7:24 ` Miles Chen
2022-12-30 5:19 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 08/23] clk: mediatek: mt8173: Migrate to platform driver and common probe AngeloGioacchino Del Regno
2022-12-30 8:22 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 09/23] clk: mediatek: mt8173: Remove mtk_clk_enable_critical() AngeloGioacchino Del Regno
2022-12-30 4:58 ` Chen-Yu Tsai
2023-01-10 12:32 ` AngeloGioacchino Del Regno
2023-01-11 2:27 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 10/23] clk: mediatek: mt8173: Break down clock drivers and allow module build AngeloGioacchino Del Regno
2022-12-24 1:47 ` kernel test robot
2022-12-24 7:13 ` Dan Carpenter
2022-12-23 9:42 ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() where possible AngeloGioacchino Del Regno
2022-12-28 7:50 ` Miles Chen
2022-12-30 5:12 ` Chen-Yu Tsai
2023-01-10 13:31 ` AngeloGioacchino Del Regno
2023-01-11 2:47 ` Chen-Yu Tsai
2023-01-11 8:56 ` [PATCH v2 11/23] clk: mediatek: Switch to mtk_clk_simple_probe() Miles Chen
2023-01-11 10:36 ` AngeloGioacchino Del Regno
2022-12-23 9:42 ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-27 16:22 ` Miles Chen
2022-12-30 7:14 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 13/23] clk: mediatek: mt8173: Migrate pericfg/topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-28 7:54 ` Miles Chen
2022-12-30 7:15 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 14/23] clk: mediatek: clk-mt8192: Move CLK_TOP_CSW_F26M_D2 in top_divs AngeloGioacchino Del Regno
2022-12-28 7:58 ` Miles Chen
2022-12-30 5:17 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 15/23] clk: mediatek: mt8192: Join top_adj_divs and top_muxes AngeloGioacchino Del Regno
2022-12-28 8:31 ` Miles Chen
2022-12-30 8:09 ` Chen-Yu Tsai
2022-12-30 8:06 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 16/23] clk: mediatek: mt8186: Join top_adj_div " AngeloGioacchino Del Regno
2022-12-30 8:17 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 17/23] clk: mediatek: clk-mt8183: Join top_aud_muxes and top_aud_divs AngeloGioacchino Del Regno
2022-12-30 8:19 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 18/23] clk: mediatek: clk-mtk: Register MFG notifier in mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-29 8:21 ` Miles Chen
2022-12-30 8:12 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 19/23] clk: mediatek: clk-mt8192: Migrate topckgen to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-30 8:18 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 20/23] clk: mediatek: clk-mt8186-topckgen: Migrate " AngeloGioacchino Del Regno
2022-12-30 5:55 ` Miles Chen
2022-12-30 8:15 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 21/23] clk: mediatek: clk-mt6795-topckgen: " AngeloGioacchino Del Regno
2022-12-30 5:56 ` Miles Chen
2022-12-30 8:13 ` Chen-Yu Tsai
2022-12-23 9:42 ` [PATCH v2 22/23] clk: mediatek: clk-mt7986-topckgen: Properly keep some clocks enabled AngeloGioacchino Del Regno
2022-12-30 5:23 ` Chen-Yu Tsai
2022-12-30 6:04 ` Miles Chen
2022-12-23 9:42 ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() AngeloGioacchino Del Regno
2022-12-27 16:18 ` [PATCH v2 12/23] clk: mediatek: clk-mtk: Extend mtk_clk_simple_probe() Miles Chen
2022-12-27 16:26 ` Miles Chen
2022-12-30 6:05 ` [PATCH v2 23/23] clk: mediatek: clk-mt7986-topckgen: Migrate to mtk_clk_simple_probe() Miles Chen
2022-12-30 8:14 ` Chen-Yu Tsai
2022-12-30 6:13 ` [PATCH v2 00/23] MediaTek clocks cleanups and improvements Miles Chen
2022-12-30 6:42 ` Chen-Yu Tsai
2022-12-30 7:19 ` Miles Chen
2023-01-03 9:36 ` Chen-Yu Tsai
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