* [PATCH 1/3] dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible
@ 2023-01-04 13:29 Konrad Dybcio
2023-01-04 13:29 ` [PATCH 2/3] arm64: dts: qcom: sm6350: Add OSM L3 node Konrad Dybcio
2023-01-04 13:29 ` [PATCH 3/3] arm64: dts: qcom: sm6350: Set up DDR & L3 scaling Konrad Dybcio
0 siblings, 2 replies; 3+ messages in thread
From: Konrad Dybcio @ 2023-01-04 13:29 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Sibi Sankar, linux-pm, devicetree,
linux-kernel
SM6350, similarly to SDM845, uses OSM hardware for L3 scaling.
Document it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
index 00afbbca9038..9d0a98d77ae9 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
@@ -22,6 +22,7 @@ properties:
- qcom,sc7180-osm-l3
- qcom,sc8180x-osm-l3
- qcom,sdm845-osm-l3
+ - qcom,sm6350-osm-l3
- qcom,sm8150-osm-l3
- const: qcom,osm-l3
- items:
--
2.39.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 2/3] arm64: dts: qcom: sm6350: Add OSM L3 node
2023-01-04 13:29 [PATCH 1/3] dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible Konrad Dybcio
@ 2023-01-04 13:29 ` Konrad Dybcio
2023-01-04 13:29 ` [PATCH 3/3] arm64: dts: qcom: sm6350: Set up DDR & L3 scaling Konrad Dybcio
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2023-01-04 13:29 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Sibi Sankar, linux-pm, devicetree,
linux-kernel
Enable the OSM block responsible for scaling the L3 cache.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index e71ffc31d41e..893a1ffb5e3d 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -2040,6 +2040,16 @@ apps_bcm_voter: bcm-voter {
};
};
+ osm_l3: interconnect@18321000 {
+ compatible = "qcom,sm6350-osm-l3", "qcom,osm-l3";
+ reg = <0x0 0x18321000 0x0 0x1000>;
+
+ clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ #interconnect-cells = <1>;
+ };
+
cpufreq_hw: cpufreq@18323000 {
compatible = "qcom,cpufreq-hw";
reg = <0 0x18323000 0 0x1000>, <0 0x18325800 0 0x1000>;
--
2.39.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* [PATCH 3/3] arm64: dts: qcom: sm6350: Set up DDR & L3 scaling
2023-01-04 13:29 [PATCH 1/3] dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible Konrad Dybcio
2023-01-04 13:29 ` [PATCH 2/3] arm64: dts: qcom: sm6350: Add OSM L3 node Konrad Dybcio
@ 2023-01-04 13:29 ` Konrad Dybcio
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2023-01-04 13:29 UTC (permalink / raw)
To: linux-arm-msm, andersson, agross, krzysztof.kozlowski
Cc: marijn.suijten, Konrad Dybcio, Georgi Djakov, Rob Herring,
Krzysztof Kozlowski, Sibi Sankar, linux-pm, devicetree,
linux-kernel
Add the CPU OPP tables including core frequency and L3 bus frequency.
The L3 throughput values were chosen by studying the frequencies
available in HW LUT and picking the highest one that's less than the
CPU frequency. DDR clock rates come from the vendor kernel.
Available values from the HW LUT:
300000000
556800000
652800000
806400000
844800000
940800000
1132800000
1209600000
1286400000
1401600000
1459200000
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm6350.dtsi | 131 +++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/sm7225.dtsi | 19 ++++
2 files changed, 150 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
index 893a1ffb5e3d..411a8279f84f 100644
--- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/interconnect/qcom,sm6350.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/mailbox/qcom-ipcc.h>
@@ -49,6 +50,9 @@ CPU0: cpu@0 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_0>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_0: l2-cache {
compatible = "cache";
@@ -68,6 +72,9 @@ CPU1: cpu@100 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_100>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_100: l2-cache {
compatible = "cache";
@@ -84,6 +91,9 @@ CPU2: cpu@200 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_200>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_200: l2-cache {
compatible = "cache";
@@ -100,6 +110,9 @@ CPU3: cpu@300 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_300>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_300: l2-cache {
compatible = "cache";
@@ -116,6 +129,9 @@ CPU4: cpu@400 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_400>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_400: l2-cache {
compatible = "cache";
@@ -132,6 +148,9 @@ CPU5: cpu@500 {
dynamic-power-coefficient = <100>;
next-level-cache = <&L2_500>;
qcom,freq-domain = <&cpufreq_hw 0>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_500: l2-cache {
compatible = "cache";
@@ -149,6 +168,9 @@ CPU6: cpu@600 {
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_600>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_600: l2-cache {
compatible = "cache";
@@ -165,6 +187,9 @@ CPU7: cpu@700 {
dynamic-power-coefficient = <703>;
next-level-cache = <&L2_700>;
qcom,freq-domain = <&cpufreq_hw 1>;
+ operating-points-v2 = <&cpu6_opp_table>;
+ interconnects = <&gem_noc MASTER_AMPSS_M0 0 &clk_virt SLAVE_EBI_CH0 0>,
+ <&osm_l3 MASTER_OSM_L3_APPS &osm_l3 SLAVE_OSM_L3>;
#cooling-cells = <2>;
L2_700: l2-cache {
compatible = "cache";
@@ -222,6 +247,112 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ /* DDR: 4-wide, 2 channels, double data rate, L3: 16-wide, 2 channels */
+ opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
+ };
+
+ opp-576000000 {
+ opp-hz = /bits/ 64 <576000000>;
+ opp-peak-kBps = <(547000 * 4 * 2 * 2) (556800 * 16 * 2)>;
+ };
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
+ };
+
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
+ };
+
+ opp-1324800000 {
+ opp-hz = /bits/ 64 <1324800000>;
+ opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1286400 * 16 * 2)>;
+ };
+
+ opp-1516800000 {
+ opp-hz = /bits/ 64 <1516800000>;
+ opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+ };
+
+ cpu6_opp_table: opp-table-cpu6 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-300000000 {
+ opp-hz = /bits/ 64 <300000000>;
+ opp-peak-kBps = <(200000 * 4 * 2 * 2) (300000 * 16 * 2)>;
+ };
+
+ opp-787200000 {
+ opp-hz = /bits/ 64 <787200000>;
+ opp-peak-kBps = <(768000 * 4 * 2 * 2) (652800 * 16 * 2)>;
+ };
+
+ opp-979200000 {
+ opp-hz = /bits/ 64 <979200000>;
+ opp-peak-kBps = <(768000 * 4 * 2 * 2) (940800 * 16 * 2)>;
+ };
+
+ opp-1036800000 {
+ opp-hz = /bits/ 64 <1036800000>;
+ opp-peak-kBps = <(1017000 * 4 * 2 * 2) (940800 * 16 * 2)>;
+ };
+
+ opp-1248000000 {
+ opp-hz = /bits/ 64 <1248000000>;
+ opp-peak-kBps = <(1017000 * 4 * 2 * 2) (1209600 * 16 * 2)>;
+ };
+
+ opp-1401600000 {
+ opp-hz = /bits/ 64 <1401600000>;
+ opp-peak-kBps = <(1353000 * 4 * 2 * 2) (1401600 * 16 * 2)>;
+ };
+
+ opp-1555200000 {
+ opp-hz = /bits/ 64 <1555200000>;
+ opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-1766400000 {
+ opp-hz = /bits/ 64 <1766400000>;
+ opp-peak-kBps = <(1555000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-2073600000 {
+ opp-hz = /bits/ 64 <2073600000>;
+ opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+ };
+
pmu {
compatible = "arm,armv8-pmuv3";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_LOW>;
diff --git a/arch/arm64/boot/dts/qcom/sm7225.dtsi b/arch/arm64/boot/dts/qcom/sm7225.dtsi
index 7b2a002ca7ff..b7b4044e9bb0 100644
--- a/arch/arm64/boot/dts/qcom/sm7225.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm7225.dtsi
@@ -14,3 +14,22 @@
&CPU5 { compatible = "qcom,kryo570"; };
&CPU6 { compatible = "qcom,kryo570"; };
&CPU7 { compatible = "qcom,kryo570"; };
+
+&cpu0_opp_table {
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <(1804000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+};
+
+&cpu6_opp_table {
+ opp-2131200000 {
+ opp-hz = /bits/ 64 <2131200000>;
+ opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+
+ opp-2208000000 {
+ opp-hz = /bits/ 64 <2208000000>;
+ opp-peak-kBps = <(2092000 * 4 * 2 * 2) (1459200 * 16 * 2)>;
+ };
+};
--
2.39.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
end of thread, other threads:[~2023-01-04 13:32 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
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2023-01-04 13:29 [PATCH 1/3] dt-bindings: interconnect: OSM L3: Add SM6350 OSM L3 compatible Konrad Dybcio
2023-01-04 13:29 ` [PATCH 2/3] arm64: dts: qcom: sm6350: Add OSM L3 node Konrad Dybcio
2023-01-04 13:29 ` [PATCH 3/3] arm64: dts: qcom: sm6350: Set up DDR & L3 scaling Konrad Dybcio
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