From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Taniya Das <quic_tdas@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org
Subject: [PATCH v3 05/12] clk: qcom: gcc-apq8084: move PLL clocks up
Date: Wed, 11 Jan 2023 08:03:55 +0200 [thread overview]
Message-ID: <20230111060402.1168726-6-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20230111060402.1168726-1-dmitry.baryshkov@linaro.org>
Move PLL clock declarations up, before clock parent tables, so that we
can use pll hw clock fields in the next commit.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
drivers/clk/qcom/gcc-apq8084.c | 162 ++++++++++++++++-----------------
1 file changed, 81 insertions(+), 81 deletions(-)
diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c
index b41f55b289ae..05a68f645115 100644
--- a/drivers/clk/qcom/gcc-apq8084.c
+++ b/drivers/clk/qcom/gcc-apq8084.c
@@ -36,6 +36,87 @@ enum {
P_SLEEP_CLK,
};
+static struct clk_pll gpll0 = {
+ .l_reg = 0x0004,
+ .m_reg = 0x0008,
+ .n_reg = 0x000c,
+ .config_reg = 0x0014,
+ .mode_reg = 0x0000,
+ .status_reg = 0x001c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll0",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll0_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(0),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll0_vote",
+ .parent_names = (const char *[]){ "gpll0" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll1 = {
+ .l_reg = 0x0044,
+ .m_reg = 0x0048,
+ .n_reg = 0x004c,
+ .config_reg = 0x0054,
+ .mode_reg = 0x0040,
+ .status_reg = 0x005c,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll1",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll1_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(1),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll1_vote",
+ .parent_names = (const char *[]){ "gpll1" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
+static struct clk_pll gpll4 = {
+ .l_reg = 0x1dc4,
+ .m_reg = 0x1dc8,
+ .n_reg = 0x1dcc,
+ .config_reg = 0x1dd4,
+ .mode_reg = 0x1dc0,
+ .status_reg = 0x1ddc,
+ .status_bit = 17,
+ .clkr.hw.init = &(struct clk_init_data){
+ .name = "gpll4",
+ .parent_names = (const char *[]){ "xo" },
+ .num_parents = 1,
+ .ops = &clk_pll_ops,
+ },
+};
+
+static struct clk_regmap gpll4_vote = {
+ .enable_reg = 0x1480,
+ .enable_mask = BIT(4),
+ .hw.init = &(struct clk_init_data){
+ .name = "gpll4_vote",
+ .parent_names = (const char *[]){ "gpll4" },
+ .num_parents = 1,
+ .ops = &clk_pll_vote_ops,
+ },
+};
+
static const struct parent_map gcc_xo_gpll0_map[] = {
{ P_XO, 0 },
{ P_GPLL0, 1 }
@@ -98,33 +179,6 @@ static const char * const gcc_xo_pcie_sleep[] = {
"sleep_clk_src",
};
-static struct clk_pll gpll0 = {
- .l_reg = 0x0004,
- .m_reg = 0x0008,
- .n_reg = 0x000c,
- .config_reg = 0x0014,
- .mode_reg = 0x0000,
- .status_reg = 0x001c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll0",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll0_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(0),
- .hw.init = &(struct clk_init_data){
- .name = "gpll0_vote",
- .parent_names = (const char *[]){ "gpll0" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static struct clk_rcg2 config_noc_clk_src = {
.cmd_rcgr = 0x0150,
.hid_width = 5,
@@ -161,60 +215,6 @@ static struct clk_rcg2 system_noc_clk_src = {
},
};
-static struct clk_pll gpll1 = {
- .l_reg = 0x0044,
- .m_reg = 0x0048,
- .n_reg = 0x004c,
- .config_reg = 0x0054,
- .mode_reg = 0x0040,
- .status_reg = 0x005c,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll1",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll1_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(1),
- .hw.init = &(struct clk_init_data){
- .name = "gpll1_vote",
- .parent_names = (const char *[]){ "gpll1" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
-static struct clk_pll gpll4 = {
- .l_reg = 0x1dc4,
- .m_reg = 0x1dc8,
- .n_reg = 0x1dcc,
- .config_reg = 0x1dd4,
- .mode_reg = 0x1dc0,
- .status_reg = 0x1ddc,
- .status_bit = 17,
- .clkr.hw.init = &(struct clk_init_data){
- .name = "gpll4",
- .parent_names = (const char *[]){ "xo" },
- .num_parents = 1,
- .ops = &clk_pll_ops,
- },
-};
-
-static struct clk_regmap gpll4_vote = {
- .enable_reg = 0x1480,
- .enable_mask = BIT(4),
- .hw.init = &(struct clk_init_data){
- .name = "gpll4_vote",
- .parent_names = (const char *[]){ "gpll4" },
- .num_parents = 1,
- .ops = &clk_pll_vote_ops,
- },
-};
-
static const struct freq_tbl ftbl_gcc_ufs_axi_clk[] = {
F(100000000, P_GPLL0, 6, 0, 0),
F(200000000, P_GPLL0, 3, 0, 0),
--
2.39.0
next prev parent reply other threads:[~2023-01-11 6:04 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-11 6:03 [PATCH v3 00/12] clock: qcom: apq8084: convert to parent_data/_hws Dmitry Baryshkov
2023-01-11 6:03 ` [PATCH v3 01/12] dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names Dmitry Baryshkov
2023-01-25 21:44 ` Stephen Boyd
2023-01-11 6:03 ` [PATCH v3 02/12] dt-bindings: clock: qcom,gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2023-01-25 21:44 ` Stephen Boyd
2023-01-11 6:03 ` [PATCH v3 03/12] dt-bindings: clock: qcom,mmcc: define clocks/clock-names for APQ8084 Dmitry Baryshkov
2023-01-25 21:45 ` Stephen Boyd
2023-01-11 6:03 ` [PATCH v3 04/12] clk: qcom: gcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2023-01-25 21:45 ` Stephen Boyd
2023-01-11 6:03 ` Dmitry Baryshkov [this message]
2023-01-25 21:46 ` [PATCH v3 05/12] clk: qcom: gcc-apq8084: move PLL clocks up Stephen Boyd
2023-01-11 6:03 ` [PATCH v3 06/12] clk: qcom: gcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2023-01-25 21:49 ` Stephen Boyd
2023-01-26 8:23 ` Dmitry Baryshkov
2023-01-11 6:03 ` [PATCH v3 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Dmitry Baryshkov
2023-01-25 21:50 ` Stephen Boyd
2023-01-26 8:25 ` Dmitry Baryshkov
2023-01-11 6:03 ` [PATCH v3 08/12] clk: qcom: mmcc-apq8084: use ARRAY_SIZE instead of specifying num_parents Dmitry Baryshkov
2023-01-25 21:50 ` Stephen Boyd
2023-01-11 6:03 ` [PATCH v3 09/12] clk: qcom: mmcc-apq8084: move clock parent tables down Dmitry Baryshkov
2023-01-25 21:50 ` Stephen Boyd
2023-01-11 6:04 ` [PATCH v3 10/12] clk: qcom: mmcc-apq8084: remove spdm clocks Dmitry Baryshkov
2023-01-25 21:50 ` Stephen Boyd
2023-01-11 6:04 ` [PATCH v3 11/12] clk: qcom: mmcc-apq8084: use parent_hws/_data instead of parent_names Dmitry Baryshkov
2023-01-25 21:51 ` Stephen Boyd
2023-01-11 6:04 ` [PATCH v3 12/12] ARM: dts: qcom: apq8084: add clocks and clock-names to gcc device Dmitry Baryshkov
2023-01-25 21:52 ` Stephen Boyd
2023-01-19 2:16 ` (subset) [PATCH v3 00/12] clock: qcom: apq8084: convert to parent_data/_hws Bjorn Andersson
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