* [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM
@ 2023-01-11 12:41 Conor Dooley
2023-01-11 12:41 ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add entry for Aldec Conor Dooley
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: Conor Dooley @ 2023-01-11 12:41 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley
Cc: Daire McNamara, devicetree, linux-riscv
Hey All,
The board has 32 GB of DDR but the DT I have access to only has a small
bit of that mapped. I tried accessing more DDR, but it was not possible
with the FPGA design as things stand. I'd rather have the devicetree
match what the vendor is shipping, so left the design/DDR as-was.
Other than fixing some minor bits from Krzysztof, the other change is
that I dropped the PCI node as that doesn't appear to be mapped.
Thanks,
Conor.
v1: https://lore.kernel.org/linux-riscv/20220906121525.3212705-1-conor.dooley@microchip.com/
Conor Dooley (3):
dt-bindings: vendor-prefixes: Add entry for Aldec
dt-bindings: riscv: microchip: document the Aldec TySoM
riscv: dts: microchip: add the Aldec TySoM's devicetree
.../devicetree/bindings/riscv/microchip.yaml | 1 +
.../devicetree/bindings/vendor-prefixes.yaml | 2 +
arch/riscv/boot/dts/microchip/Makefile | 1 +
.../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++
.../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 ++++++++++++++++++
5 files changed, 216 insertions(+)
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi
create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts
--
2.39.0
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add entry for Aldec 2023-01-11 12:41 [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley @ 2023-01-11 12:41 ` Conor Dooley 2023-01-11 12:41 ` [PATCH v2 2/3] dt-bindings: riscv: microchip: document the Aldec TySoM Conor Dooley ` (2 subsequent siblings) 3 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2023-01-11 12:41 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Daire McNamara, devicetree, linux-riscv, Krzysztof Kozlowski Per their website: Aldec, Inc. is an industry-leading Electronic Design Automation (EDA) company delivering innovative design creation, simulation and verification solutions to assist in the development of complex FPGA, ASIC, SoC and embedded system designs. Link: https://www.aldec.com/ Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 70ffb3780621..d119e9a7c287 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -69,6 +69,8 @@ patternProperties: description: Annapurna Labs "^alcatel,.*": description: Alcatel + "^aldec,.*": + description: Aldec, Inc. "^alfa-network,.*": description: ALFA Network Inc. "^allegro,.*": -- 2.39.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 2/3] dt-bindings: riscv: microchip: document the Aldec TySoM 2023-01-11 12:41 [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley 2023-01-11 12:41 ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add entry for Aldec Conor Dooley @ 2023-01-11 12:41 ` Conor Dooley 2023-01-11 12:41 ` [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree Conor Dooley 2023-01-20 22:21 ` [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley 3 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2023-01-11 12:41 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Daire McNamara, devicetree, linux-riscv, Krzysztof Kozlowski The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Document rev2 of this board. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Changes in v2: - added rev2 to the compatible. I kept the ack as you can tell Krzysztof --- Documentation/devicetree/bindings/riscv/microchip.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 714d0fcab399..4a29c890619a 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -27,6 +27,7 @@ properties: - items: - enum: + - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp - microchip,mpfs-sev-kit - sundance,polarberry -- 2.39.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree 2023-01-11 12:41 [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley 2023-01-11 12:41 ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add entry for Aldec Conor Dooley 2023-01-11 12:41 ` [PATCH v2 2/3] dt-bindings: riscv: microchip: document the Aldec TySoM Conor Dooley @ 2023-01-11 12:41 ` Conor Dooley 2023-01-11 12:47 ` Conor.Dooley 2023-01-20 22:21 ` [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley 3 siblings, 1 reply; 6+ messages in thread From: Conor Dooley @ 2023-01-11 12:41 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: Daire McNamara, devicetree, linux-riscv The TySOM-M-MPFS250 is a compact SoC prototyping board featuring a Microchip PolarFire SoC MPFS250T-FCG1152. Features include: - 16 GiB FPGA DDR4 - 16 GiB MSS DDR4 with ECC (Although only 2 GiB is mapped in the FPGA design) - eMMC - SPI flash memory - 2x Ethernet 10/100/1000 - USB 2.0 - PCIe x4 Gen2 - HDMI OUT - 2x FMC connector (HPC and LPC) Specifically flag this board as rev2, in case later boards have an FPGA design revision with more of DDR available for use in Linux etc. Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 Signed-off-by: Conor Dooley <conor.dooley@microchip.com> --- Changes in v2: - removed some extra cells properties - changed filename compatible to rev2 - dropped pcie from fabric.dtsi, does not appear to be mapped to the MSS --- arch/riscv/boot/dts/microchip/Makefile | 1 + .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++ .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 ++++++++++++++++++ 3 files changed, 213 insertions(+) create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile index 7427a20934f3..c54922a325fd 100644 --- a/arch/riscv/boot/dts/microchip/Makefile +++ b/arch/riscv/boot/dts/microchip/Makefile @@ -3,4 +3,5 @@ dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi new file mode 100644 index 000000000000..51d0c5176b9e --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* Copyright (c) 2022 Microchip Technology Inc */ + +// #include "dt-bindings/mailbox/miv-ihc.h" + +/ { + fabric_clk3: fabric-clk3 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <62500000>; + }; + + fabric_clk1: fabric-clk1 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + + pcie: pcie@2000000000 { + compatible = "microchip,pcie-host-1.0"; + #address-cells = <0x3>; + #interrupt-cells = <0x1>; + #size-cells = <0x2>; + device_type = "pci"; + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; + reg-names = "cfg", "apb"; + bus-range = <0x0 0x7f>; + interrupt-parent = <&plic>; + interrupts = <119>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + interrupt-map-mask = <0 0 0 7>; + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; + clock-names = "fic0", "fic1", "fic3"; + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; + msi-parent = <&pcie>; + msi-controller; + status = "disabled"; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; +}; diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts new file mode 100644 index 000000000000..e0797c7e1b35 --- /dev/null +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts @@ -0,0 +1,165 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Original all-in-one devicetree: + * Copyright (C) 2020-2022 - Aldec + * Rewritten to use includes: + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> + */ + +/dts-v1/; + +#include "mpfs.dtsi" +#include "mpfs-tysom-m-fabric.dtsi" + +/* Clock frequency (in Hz) of the rtcclk */ +#define MTIMER_FREQ 1000000 + +/ { + model = "Aldec TySOM-M-MPFS250T-REV2"; + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; + + aliases { + ethernet0 = &mac0; + ethernet1 = &mac1; + serial0 = &mmuart0; + serial1 = &mmuart1; + serial2 = &mmuart2; + serial3 = &mmuart3; + serial4 = &mmuart4; + gpio0 = &gpio0; + gpio1 = &gpio2; + }; + + chosen { + stdout-path = "serial1:115200n8"; + }; + + cpus { + timebase-frequency = <MTIMER_FREQ>; + }; + + ddrc_cache_lo: memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x0 0x30000000>; + status = "okay"; + }; + + ddrc_cache_hi: memory@1000000000 { + device_type = "memory"; + reg = <0x10 0x00000000 0x0 0x40000000>; + status = "okay"; + }; + + leds { + compatible = "gpio-leds"; + status = "okay"; + + led0 { + gpios = <&gpio1 23 1>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c1 { + status = "okay"; + hwmon: hwmon@45 { + status = "okay"; + compatible = "ti,ina219"; + reg = <0x45>; + shunt-resistor = <2000>; + }; +}; + +&gpio1 { + interrupts = <27>, <28>, <29>, <30>, + <31>, <32>, <33>, <47>, + <35>, <36>, <37>, <38>, + <39>, <40>, <41>, <42>, + <43>, <44>, <45>, <46>, + <47>, <48>, <49>, <50>; + status = "okay"; +}; + +&mac0 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy0>; + +}; + +&mac1 { + status = "okay"; + phy-mode = "gmii"; + phy-handle = <&phy1>; + phy1: ethernet-phy@1 { + reg = <1>; + }; + phy0: ethernet-phy@0 { + reg = <0>; + }; +}; + +&mbox { + status = "okay"; +}; + +&mmc { + max-frequency = <200000000>; + cap-mmc-highspeed; + cap-sd-highspeed; + no-1-8-v; + disable-wp; + status = "okay"; +}; + +&mmuart1 { + status = "okay"; +}; + +&mmuart2 { + status = "okay"; +}; + +&mmuart3 { + status = "okay"; +}; + +&mmuart4 { + status = "okay"; +}; + +&refclk { + clock-frequency = <125000000>; +}; + +&rtc { + status = "okay"; +}; + +&spi0 { + status = "okay"; +}; + +&spi1 { + status = "okay"; + flash@0 { + compatible = "micron,n25q128a11", "jedec,spi-nor"; + reg = <0x0>; + spi-max-frequency = <10000000>; + }; +}; + +&syscontroller { + status = "okay"; +}; + +&usb { + status = "okay"; + dr_mode = "host"; +}; -- 2.39.0 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree 2023-01-11 12:41 ` [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree Conor Dooley @ 2023-01-11 12:47 ` Conor.Dooley 0 siblings, 0 replies; 6+ messages in thread From: Conor.Dooley @ 2023-01-11 12:47 UTC (permalink / raw) To: Conor.Dooley Cc: Daire.McNamara, robh+dt, devicetree, linux-riscv, krzysztof.kozlowski+dt On 11/01/2023 12:41, Conor Dooley wrote: > The TySOM-M-MPFS250 is a compact SoC prototyping board featuring > a Microchip PolarFire SoC MPFS250T-FCG1152. Features include: > - 16 GiB FPGA DDR4 > - 16 GiB MSS DDR4 with ECC (Although only 2 GiB is mapped in the > FPGA design) > - eMMC > - SPI flash memory > - 2x Ethernet 10/100/1000 > - USB 2.0 > - PCIe x4 Gen2 > - HDMI OUT > - 2x FMC connector (HPC and LPC) > > Specifically flag this board as rev2, in case later boards have an > FPGA design revision with more of DDR available for use in Linux etc. > > Link: https://www.aldec.com/en/products/emulation/tysom_boards/polarfire_microchip/tysom_m_mpfs250 > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > --- > Changes in v2: > - removed some extra cells properties > - changed filename compatible to rev2 > - dropped pcie from fabric.dtsi, does not appear to be mapped to the MSS Heh, no I didn't. Meant to though! Removing it will have no functional change though, as it is disabled. I won't resend to drop it, unless something else needs to be changed. > --- > arch/riscv/boot/dts/microchip/Makefile | 1 + > .../dts/microchip/mpfs-tysom-m-fabric.dtsi | 47 +++++ > .../riscv/boot/dts/microchip/mpfs-tysom-m.dts | 165 ++++++++++++++++++ > 3 files changed, 213 insertions(+) > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi > create mode 100644 arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts > > diff --git a/arch/riscv/boot/dts/microchip/Makefile b/arch/riscv/boot/dts/microchip/Makefile > index 7427a20934f3..c54922a325fd 100644 > --- a/arch/riscv/boot/dts/microchip/Makefile > +++ b/arch/riscv/boot/dts/microchip/Makefile > @@ -3,4 +3,5 @@ dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-icicle-kit.dtb > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-m100pfsevp.dtb > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-polarberry.dtb > dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-sev-kit.dtb > +dtb-$(CONFIG_SOC_MICROCHIP_POLARFIRE) += mpfs-tysom-m.dtb > obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y)) > diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi > new file mode 100644 > index 000000000000..51d0c5176b9e > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m-fabric.dtsi > @@ -0,0 +1,47 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* Copyright (c) 2022 Microchip Technology Inc */ > + > +// #include "dt-bindings/mailbox/miv-ihc.h" > + > +/ { > + fabric_clk3: fabric-clk3 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <62500000>; > + }; > + > + fabric_clk1: fabric-clk1 { > + compatible = "fixed-clock"; > + #clock-cells = <0>; > + clock-frequency = <125000000>; > + }; > + > + pcie: pcie@2000000000 { > + compatible = "microchip,pcie-host-1.0"; > + #address-cells = <0x3>; > + #interrupt-cells = <0x1>; > + #size-cells = <0x2>; > + device_type = "pci"; > + reg = <0x20 0x0 0x0 0x8000000>, <0x0 0x43000000 0x0 0x10000>; > + reg-names = "cfg", "apb"; > + bus-range = <0x0 0x7f>; > + interrupt-parent = <&plic>; > + interrupts = <119>; > + interrupt-map = <0 0 0 1 &pcie_intc 0>, > + <0 0 0 2 &pcie_intc 1>, > + <0 0 0 3 &pcie_intc 2>, > + <0 0 0 4 &pcie_intc 3>; > + interrupt-map-mask = <0 0 0 7>; > + clocks = <&fabric_clk1>, <&fabric_clk1>, <&fabric_clk3>; > + clock-names = "fic0", "fic1", "fic3"; > + ranges = <0x3000000 0x0 0x8000000 0x20 0x8000000 0x0 0x80000000>; > + msi-parent = <&pcie>; > + msi-controller; > + status = "disabled"; > + pcie_intc: interrupt-controller { > + #address-cells = <0>; > + #interrupt-cells = <1>; > + interrupt-controller; > + }; > + }; > +}; > diff --git a/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts > new file mode 100644 > index 000000000000..e0797c7e1b35 > --- /dev/null > +++ b/arch/riscv/boot/dts/microchip/mpfs-tysom-m.dts > @@ -0,0 +1,165 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Original all-in-one devicetree: > + * Copyright (C) 2020-2022 - Aldec > + * Rewritten to use includes: > + * Copyright (C) 2022 - Conor Dooley <conor.dooley@microchip.com> > + */ > + > +/dts-v1/; > + > +#include "mpfs.dtsi" > +#include "mpfs-tysom-m-fabric.dtsi" > + > +/* Clock frequency (in Hz) of the rtcclk */ > +#define MTIMER_FREQ 1000000 > + > +/ { > + model = "Aldec TySOM-M-MPFS250T-REV2"; > + compatible = "aldec,tysom-m-mpfs250t-rev2", "microchip,mpfs"; > + > + aliases { > + ethernet0 = &mac0; > + ethernet1 = &mac1; > + serial0 = &mmuart0; > + serial1 = &mmuart1; > + serial2 = &mmuart2; > + serial3 = &mmuart3; > + serial4 = &mmuart4; > + gpio0 = &gpio0; > + gpio1 = &gpio2; > + }; > + > + chosen { > + stdout-path = "serial1:115200n8"; > + }; > + > + cpus { > + timebase-frequency = <MTIMER_FREQ>; > + }; > + > + ddrc_cache_lo: memory@80000000 { > + device_type = "memory"; > + reg = <0x0 0x80000000 0x0 0x30000000>; > + status = "okay"; > + }; > + > + ddrc_cache_hi: memory@1000000000 { > + device_type = "memory"; > + reg = <0x10 0x00000000 0x0 0x40000000>; > + status = "okay"; > + }; > + > + leds { > + compatible = "gpio-leds"; > + status = "okay"; > + > + led0 { > + gpios = <&gpio1 23 1>; > + default-state = "on"; > + linux,default-trigger = "heartbeat"; > + }; > + }; > +}; > + > +&i2c0 { > + status = "okay"; > +}; > + > +&i2c1 { > + status = "okay"; > + hwmon: hwmon@45 { > + status = "okay"; > + compatible = "ti,ina219"; > + reg = <0x45>; > + shunt-resistor = <2000>; > + }; > +}; > + > +&gpio1 { > + interrupts = <27>, <28>, <29>, <30>, > + <31>, <32>, <33>, <47>, > + <35>, <36>, <37>, <38>, > + <39>, <40>, <41>, <42>, > + <43>, <44>, <45>, <46>, > + <47>, <48>, <49>, <50>; > + status = "okay"; > +}; > + > +&mac0 { > + status = "okay"; > + phy-mode = "gmii"; > + phy-handle = <&phy0>; > + > +}; > + > +&mac1 { > + status = "okay"; > + phy-mode = "gmii"; > + phy-handle = <&phy1>; > + phy1: ethernet-phy@1 { > + reg = <1>; > + }; > + phy0: ethernet-phy@0 { > + reg = <0>; > + }; > +}; > + > +&mbox { > + status = "okay"; > +}; > + > +&mmc { > + max-frequency = <200000000>; > + cap-mmc-highspeed; > + cap-sd-highspeed; > + no-1-8-v; > + disable-wp; > + status = "okay"; > +}; > + > +&mmuart1 { > + status = "okay"; > +}; > + > +&mmuart2 { > + status = "okay"; > +}; > + > +&mmuart3 { > + status = "okay"; > +}; > + > +&mmuart4 { > + status = "okay"; > +}; > + > +&refclk { > + clock-frequency = <125000000>; > +}; > + > +&rtc { > + status = "okay"; > +}; > + > +&spi0 { > + status = "okay"; > +}; > + > +&spi1 { > + status = "okay"; > + flash@0 { > + compatible = "micron,n25q128a11", "jedec,spi-nor"; > + reg = <0x0>; > + spi-max-frequency = <10000000>; > + }; > +}; > + > +&syscontroller { > + status = "okay"; > +}; > + > +&usb { > + status = "okay"; > + dr_mode = "host"; > +}; ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM 2023-01-11 12:41 [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley ` (2 preceding siblings ...) 2023-01-11 12:41 ` [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree Conor Dooley @ 2023-01-20 22:21 ` Conor Dooley 3 siblings, 0 replies; 6+ messages in thread From: Conor Dooley @ 2023-01-20 22:21 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley Cc: conor, Daire McNamara, devicetree, linux-riscv From: Conor Dooley <conor.dooley@microchip.com> On Wed, 11 Jan 2023 12:41:04 +0000, Conor Dooley wrote: > Hey All, > > The board has 32 GB of DDR but the DT I have access to only has a small > bit of that mapped. I tried accessing more DDR, but it was not possible > with the FPGA design as things stand. I'd rather have the devicetree > match what the vendor is shipping, so left the design/DDR as-was. > > [...] Applied to riscv-dt-for-next, thanks! [1/3] dt-bindings: vendor-prefixes: Add entry for Aldec https://git.kernel.org/conor/c/f6beee9118c3 [2/3] dt-bindings: riscv: microchip: document the Aldec TySoM https://git.kernel.org/conor/c/ea913d8865fe [3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree https://git.kernel.org/conor/c/4f7d64156292 Removed the PCIe that I forgot to remove before sending in the process... Thanks, Conor. ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2023-01-20 22:22 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-01-11 12:41 [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley 2023-01-11 12:41 ` [PATCH v2 1/3] dt-bindings: vendor-prefixes: Add entry for Aldec Conor Dooley 2023-01-11 12:41 ` [PATCH v2 2/3] dt-bindings: riscv: microchip: document the Aldec TySoM Conor Dooley 2023-01-11 12:41 ` [PATCH v2 3/3] riscv: dts: microchip: add the Aldec TySoM's devicetree Conor Dooley 2023-01-11 12:47 ` Conor.Dooley 2023-01-20 22:21 ` [PATCH v2 0/3] Add a devicetree for the Aldec PolarFire SoC TySoM Conor Dooley
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).