[V1,0/2] Add jpeg enc & dec device node for MT8195

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* [V1,0/2] Add jpeg enc & dec device node for MT8195
@ 2023-01-12  8:45 Irui Wang
  2023-01-12  8:45 ` [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Irui Wang
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Irui Wang @ 2023-01-12  8:45 UTC (permalink / raw)
  To: Hans Verkuil, Rob Herring, Krzysztof Kozlowski,
	Mauro Carvalho Chehab, Matthias Brugger,
	angelogioacchino.delregno, nicolas.dufresne, kyrie wu
  Cc: Project_Global_Chrome_Upstream_Group, devicetree, linux-media,
	linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
	xia.jiang, maoguang.meng, Irui Wang

From: kyrie wu <kyrie.wu@mediatek.com>

This series add jpeg enc and dec device node to dts file
for the purpose of supporting multi hardwares jpeg
enc & dec of MT8195.

This series has been tested with MT8195 Gstreamer.
Encoding and decoding worked for this chip.

Patches 1 Adds jpeg encoder device node for mt8195.

Patches 2 Adds jpeg decoder device node for mt8195.

kyrie wu (2):
  arm64: dts: mt8195: add jpeg encode device node
  arm64: dts: mt8195: add jpeg decode device node

 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 100 +++++++++++++++++++++++
 1 file changed, 100 insertions(+)

-- 
2.18.0


^ permalink raw reply	[flat|nested] 4+ messages in thread

* [V1,1/2] arm64: dts: mt8195: add jpeg encode device node
  2023-01-12  8:45 [V1,0/2] Add jpeg enc & dec device node for MT8195 Irui Wang
@ 2023-01-12  8:45 ` Irui Wang
  2023-01-12  8:45 ` [V1,2/2] arm64: dts: mt8195: add jpeg decode " Irui Wang
  2023-01-25 15:22 ` [V1,0/2] Add jpeg enc & dec device node for MT8195 Matthias Brugger
  2 siblings, 0 replies; 4+ messages in thread
From: Irui Wang @ 2023-01-12  8:45 UTC (permalink / raw)
  To: Hans Verkuil, Rob Herring, Krzysztof Kozlowski,
	Mauro Carvalho Chehab, Matthias Brugger,
	angelogioacchino.delregno, nicolas.dufresne, kyrie wu
  Cc: Project_Global_Chrome_Upstream_Group, devicetree, linux-media,
	linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
	xia.jiang, maoguang.meng, Irui Wang

From: kyrie wu <kyrie.wu@mediatek.com>

add mt8195 jpegenc device node

Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: irui wang <irui.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 40 ++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 5d31536f4c48..af49ec352bfe 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2152,6 +2152,46 @@
 			#clock-cells = <1>;
 		};
 
+
+		jpgenc-master {
+			compatible = "mediatek,mt8195-jpgenc";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+			iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
+					<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
+					<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
+					<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			jpgenc@1a030000 {
+				compatible = "mediatek,mt8195-jpgenc-hw";
+				reg = <0 0x1a030000 0 0x10000>;
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGENC_Y_RDMA>,
+						<&iommu_vdo M4U_PORT_L19_JPGENC_C_RDMA>,
+						<&iommu_vdo M4U_PORT_L19_JPGENC_Q_TABLE>,
+						<&iommu_vdo M4U_PORT_L19_JPGENC_BSDMA>;
+				interrupts = <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGENC>;
+				clock-names = "jpgenc";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+			};
+
+			jpgenc@1b030000 {
+				compatible = "mediatek,mt8195-jpgenc-hw";
+				reg = <0 0x1b030000 0 0x10000>;
+				iommus = <&iommu_vpp M4U_PORT_L20_JPGENC_Y_RDMA>,
+						<&iommu_vpp M4U_PORT_L20_JPGENC_C_RDMA>,
+						<&iommu_vpp M4U_PORT_L20_JPGENC_Q_TABLE>,
+						<&iommu_vpp M4U_PORT_L20_JPGENC_BSDMA>;
+				interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGENC>;
+				clock-names = "jpgenc";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+			};
+		};
+
 		larb20: larb@1b010000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x1b010000 0 0x1000>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [V1,2/2] arm64: dts: mt8195: add jpeg decode device node
  2023-01-12  8:45 [V1,0/2] Add jpeg enc & dec device node for MT8195 Irui Wang
  2023-01-12  8:45 ` [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Irui Wang
@ 2023-01-12  8:45 ` Irui Wang
  2023-01-25 15:22 ` [V1,0/2] Add jpeg enc & dec device node for MT8195 Matthias Brugger
  2 siblings, 0 replies; 4+ messages in thread
From: Irui Wang @ 2023-01-12  8:45 UTC (permalink / raw)
  To: Hans Verkuil, Rob Herring, Krzysztof Kozlowski,
	Mauro Carvalho Chehab, Matthias Brugger,
	angelogioacchino.delregno, nicolas.dufresne, kyrie wu
  Cc: Project_Global_Chrome_Upstream_Group, devicetree, linux-media,
	linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
	xia.jiang, maoguang.meng, Irui Wang

From: kyrie wu <kyrie.wu@mediatek.com>

add mt8195 jpegdec device node

Signed-off-by: kyrie wu <kyrie.wu@mediatek.com>
Signed-off-by: irui wang <irui.wang@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt8195.dtsi | 60 ++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index af49ec352bfe..d5d0aeac57e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -2192,6 +2192,66 @@
 			};
 		};
 
+		jpgdec-master {
+			compatible = "mediatek,mt8195-jpgdec";
+			power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+					<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+			dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			jpgdec@1a040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a040000 0 0x10000>;/* JPGDEC_C0 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+			};
+
+			jpgdec@1a050000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1a050000 0 0x10000>;/* JPGDEC_C1 */
+				iommus = <&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA0>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_WDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BSDMA1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vdo M4U_PORT_L19_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys CLK_VENC_JPGDEC_C1>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+			};
+
+			jpgdec@1b040000 {
+				compatible = "mediatek,mt8195-jpgdec-hw";
+				reg = <0 0x1b040000 0 0x10000>;/* JPGDEC_C2 */
+				iommus = <&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA0>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_WDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BSDMA1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET1>,
+						<&iommu_vpp M4U_PORT_L20_JPGDEC_BUFF_OFFSET0>;
+				interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH 0>;
+				clocks = <&vencsys_core1 CLK_VENC_CORE1_JPGDEC>;
+				clock-names = "jpgdec";
+				power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+			};
+		};
+
 		larb20: larb@1b010000 {
 			compatible = "mediatek,mt8195-smi-larb";
 			reg = <0 0x1b010000 0 0x1000>;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [V1,0/2] Add jpeg enc & dec device node for MT8195
  2023-01-12  8:45 [V1,0/2] Add jpeg enc & dec device node for MT8195 Irui Wang
  2023-01-12  8:45 ` [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Irui Wang
  2023-01-12  8:45 ` [V1,2/2] arm64: dts: mt8195: add jpeg decode " Irui Wang
@ 2023-01-25 15:22 ` Matthias Brugger
  2 siblings, 0 replies; 4+ messages in thread
From: Matthias Brugger @ 2023-01-25 15:22 UTC (permalink / raw)
  To: Irui Wang, Hans Verkuil, Rob Herring, Krzysztof Kozlowski,
	Mauro Carvalho Chehab, angelogioacchino.delregno,
	nicolas.dufresne, kyrie wu
  Cc: Project_Global_Chrome_Upstream_Group, devicetree, linux-media,
	linux-kernel, linux-arm-kernel, linux-mediatek, Tomasz Figa,
	xia.jiang, maoguang.meng

Applied, thanks!

On 12/01/2023 09:45, Irui Wang wrote:
> From: kyrie wu <kyrie.wu@mediatek.com>
> 
> This series add jpeg enc and dec device node to dts file
> for the purpose of supporting multi hardwares jpeg
> enc & dec of MT8195.
> 
> This series has been tested with MT8195 Gstreamer.
> Encoding and decoding worked for this chip.
> 
> Patches 1 Adds jpeg encoder device node for mt8195.
> 
> Patches 2 Adds jpeg decoder device node for mt8195.
> 
> kyrie wu (2):
>    arm64: dts: mt8195: add jpeg encode device node
>    arm64: dts: mt8195: add jpeg decode device node
> 
>   arch/arm64/boot/dts/mediatek/mt8195.dtsi | 100 +++++++++++++++++++++++
>   1 file changed, 100 insertions(+)
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2023-01-25 15:22 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-01-12  8:45 [V1,0/2] Add jpeg enc & dec device node for MT8195 Irui Wang
2023-01-12  8:45 ` [V1,1/2] arm64: dts: mt8195: add jpeg encode device node Irui Wang
2023-01-12  8:45 ` [V1,2/2] arm64: dts: mt8195: add jpeg decode " Irui Wang
2023-01-25 15:22 ` [V1,0/2] Add jpeg enc & dec device node for MT8195 Matthias Brugger

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