* [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver [not found] <20230116093845.72621-1-konrad.dybcio@linaro.org> @ 2023-01-16 9:38 ` Konrad Dybcio 2023-01-16 9:43 ` Konrad Dybcio ` (2 more replies) 2023-01-16 9:38 ` [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio 2023-01-16 9:38 ` [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio 2 siblings, 3 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 9:38 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, Konrad Dybcio, AngeloGioacchino Del Regno, Rob Herring, Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Add the bindings for the CPR3 driver to the documentation. Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Konrad: Make binding check pass; update AGdR's email] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- .../bindings/soc/qcom/qcom,cpr3.yaml | 314 ++++++++++++++++++ 1 file changed, 314 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml new file mode 100644 index 000000000000..eb11af375e54 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml @@ -0,0 +1,314 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#" +$schema: "http://devicetree.org/meta-schemas/core.yaml#" + +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) + +description: | + CPR (Core Power Reduction) is a technology to reduce core power on a CPU + or other device. Each OPP of a device corresponds to a "corner" that has + a range of valid voltages for a particular frequency. While the device is + running at a particular frequency, CPR monitors dynamic factors such as + temperature, etc. and suggests or, in the CPR-Hardened case performs, + adjustments to the voltage to save power and meet silicon characteristic + requirements. + +maintainers: + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> + +properties: + compatible: + oneOf: + - description: CPRv3 controller + items: + - const: qcom,cpr3 + - description: CPRv4 controller + items: + - const: qcom,cpr4 + - description: CPRv4-Hardened controller + items: + - enum: + - qcom,msm8998-cprh + - qcom,sdm630-cprh + - const: qcom,cprh + + reg: + description: Base address and size of the CPR controller(s) + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + clock-names: + items: + - const: "ref" + + clocks: + items: + - description: CPR reference clock + + vdd-supply: + description: Autonomous Phase Control (APC) or other power supply + + '#power-domain-cells': + const: 1 + + acc-syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to syscon for writing ACC settings + + nvmem-cells: + description: Cells containing the fuse corners and revision data + minItems: 10 + maxItems: 32 + + nvmem-cell-names: + minItems: 10 + maxItems: 32 + + operating-points-v2: true + + power-domains: true + +required: + - compatible + - reg + - clocks + - clock-names + - operating-points-v2 + - "#power-domain-cells" + - nvmem-cells + - nvmem-cell-names + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + contains: + enum: + - qcom,msm8998-cprh + then: + properties: + nvmem-cell-names: + items: + - const: "cpr_speed_bin" + - const: "cpr_fuse_revision" + - const: "cpr0_quotient1" + - const: "cpr0_quotient2" + - const: "cpr0_quotient3" + - const: "cpr0_quotient4" + - const: "cpr0_quotient_offset2" + - const: "cpr0_quotient_offset3" + - const: "cpr0_quotient_offset4" + - const: "cpr0_init_voltage1" + - const: "cpr0_init_voltage2" + - const: "cpr0_init_voltage3" + - const: "cpr0_init_voltage4" + - const: "cpr0_ring_osc1" + - const: "cpr0_ring_osc2" + - const: "cpr0_ring_osc3" + - const: "cpr0_ring_osc4" + - const: "cpr1_quotient1" + - const: "cpr1_quotient2" + - const: "cpr1_quotient3" + - const: "cpr1_quotient4" + - const: "cpr1_quotient_offset2" + - const: "cpr1_quotient_offset3" + - const: "cpr1_quotient_offset4" + - const: "cpr1_init_voltage1" + - const: "cpr1_init_voltage2" + - const: "cpr1_init_voltage3" + - const: "cpr1_init_voltage4" + - const: "cpr1_ring_osc1" + - const: "cpr1_ring_osc2" + - const: "cpr1_ring_osc3" + - const: "cpr1_ring_osc4" + else: + items: + - const: "cpr_quotient_offset1" + - const: "cpr_quotient_offset2" + - const: "cpr_quotient_offset3" + - const: "cpr_init_voltage1" + - const: "cpr_init_voltage2" + - const: "cpr_init_voltage3" + - const: "cpr_quotient1" + - const: "cpr_quotient2" + - const: "cpr_quotient3" + - const: "cpr_ring_osc1" + - const: "cpr_ring_osc2" + - const: "cpr_ring_osc3" + - const: "cpr_fuse_revision" + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-msm8998.h> + #include <dt-bindings/interrupt-controller/irq.h> + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x0>; + operating-points-v2 = <&cpu_gold_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; + }; + + cpu@100 { + compatible = "qcom,kryo280"; + device_type = "cpu"; + reg = <0x0 0x100>; + operating-points-v2 = <&cpu_silver_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1843200000 { + opp-hz = /bits/ 64 <1843200000>; + required-opps = <&cprh_opp3>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cprh_opp2>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cprh_opp3>; + }; + + opp-1113600000 { + opp-hz = /bits/ 64 <1113600000>; + required-opps = <&cprh_opp2>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + }; + }; + + cprh_opp_table: opp-table-cprh { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp1: opp-1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp2: opp-2 { + opp-level = <2>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp3: opp-3 { + opp-level = <3>; + qcom,opp-fuse-level = <2 3>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + }; + + apc_cprh: power-controller@179c8000 { + compatible = "qcom,msm8998-cprh", "qcom,cprh"; + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "ref"; + + operating-points-v2 = <&cprh_opp_table>; + #power-domain-cells = <1>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>, + <&cpr_quot0_perfcl>, + <&cpr_quot1_perfcl>, + <&cpr_quot2_perfcl>, + <&cpr_quot3_perfcl>, + <&cpr_quot_offset1_perfcl>, + <&cpr_quot_offset2_perfcl>, + <&cpr_quot_offset3_perfcl>, + <&cpr_init_voltage0_perfcl>, + <&cpr_init_voltage1_perfcl>, + <&cpr_init_voltage2_perfcl>, + <&cpr_init_voltage3_perfcl>, + <&cpr_ro_sel0_perfcl>, + <&cpr_ro_sel1_perfcl>, + <&cpr_ro_sel2_perfcl>, + <&cpr_ro_sel3_perfcl>; + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4", + "cpr1_quotient1", + "cpr1_quotient2", + "cpr1_quotient3", + "cpr1_quotient4", + "cpr1_quotient_offset2", + "cpr1_quotient_offset3", + "cpr1_quotient_offset4", + "cpr1_init_voltage1", + "cpr1_init_voltage2", + "cpr1_init_voltage3", + "cpr1_init_voltage4", + "cpr1_ring_osc1", + "cpr1_ring_osc2", + "cpr1_ring_osc3", + "cpr1_ring_osc4"; + }; +... -- 2.39.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver 2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio @ 2023-01-16 9:43 ` Konrad Dybcio 2023-01-16 11:26 ` Konrad Dybcio 2023-01-16 16:36 ` Rob Herring 2 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 9:43 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, AngeloGioacchino Del Regno, Rob Herring, Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel On 16.01.2023 10:38, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Add the bindings for the CPR3 driver to the documentation. > > Reviewed-by: Rob Herring <robh@kernel.org> Eh... forgive me, I said I dropped it in the cover letter, but forgot to do actually it in the patch after all.. Konrad > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > [Konrad: Make binding check pass; update AGdR's email] > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../bindings/soc/qcom/qcom,cpr3.yaml | 314 ++++++++++++++++++ > 1 file changed, 314 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > new file mode 100644 > index 000000000000..eb11af375e54 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > @@ -0,0 +1,314 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) > + > +description: | > + CPR (Core Power Reduction) is a technology to reduce core power on a CPU > + or other device. Each OPP of a device corresponds to a "corner" that has > + a range of valid voltages for a particular frequency. While the device is > + running at a particular frequency, CPR monitors dynamic factors such as > + temperature, etc. and suggests or, in the CPR-Hardened case performs, > + adjustments to the voltage to save power and meet silicon characteristic > + requirements. > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + > +properties: > + compatible: > + oneOf: > + - description: CPRv3 controller > + items: > + - const: qcom,cpr3 > + - description: CPRv4 controller > + items: > + - const: qcom,cpr4 > + - description: CPRv4-Hardened controller > + items: > + - enum: > + - qcom,msm8998-cprh > + - qcom,sdm630-cprh > + - const: qcom,cprh > + > + reg: > + description: Base address and size of the CPR controller(s) > + minItems: 1 > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + clock-names: > + items: > + - const: "ref" > + > + clocks: > + items: > + - description: CPR reference clock > + > + vdd-supply: > + description: Autonomous Phase Control (APC) or other power supply > + > + '#power-domain-cells': > + const: 1 > + > + acc-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to syscon for writing ACC settings > + > + nvmem-cells: > + description: Cells containing the fuse corners and revision data > + minItems: 10 > + maxItems: 32 > + > + nvmem-cell-names: > + minItems: 10 > + maxItems: 32 > + > + operating-points-v2: true > + > + power-domains: true > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - operating-points-v2 > + - "#power-domain-cells" > + - nvmem-cells > + - nvmem-cell-names > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,msm8998-cprh > + then: > + properties: > + nvmem-cell-names: > + items: > + - const: "cpr_speed_bin" > + - const: "cpr_fuse_revision" > + - const: "cpr0_quotient1" > + - const: "cpr0_quotient2" > + - const: "cpr0_quotient3" > + - const: "cpr0_quotient4" > + - const: "cpr0_quotient_offset2" > + - const: "cpr0_quotient_offset3" > + - const: "cpr0_quotient_offset4" > + - const: "cpr0_init_voltage1" > + - const: "cpr0_init_voltage2" > + - const: "cpr0_init_voltage3" > + - const: "cpr0_init_voltage4" > + - const: "cpr0_ring_osc1" > + - const: "cpr0_ring_osc2" > + - const: "cpr0_ring_osc3" > + - const: "cpr0_ring_osc4" > + - const: "cpr1_quotient1" > + - const: "cpr1_quotient2" > + - const: "cpr1_quotient3" > + - const: "cpr1_quotient4" > + - const: "cpr1_quotient_offset2" > + - const: "cpr1_quotient_offset3" > + - const: "cpr1_quotient_offset4" > + - const: "cpr1_init_voltage1" > + - const: "cpr1_init_voltage2" > + - const: "cpr1_init_voltage3" > + - const: "cpr1_init_voltage4" > + - const: "cpr1_ring_osc1" > + - const: "cpr1_ring_osc2" > + - const: "cpr1_ring_osc3" > + - const: "cpr1_ring_osc4" > + else: > + items: > + - const: "cpr_quotient_offset1" > + - const: "cpr_quotient_offset2" > + - const: "cpr_quotient_offset3" > + - const: "cpr_init_voltage1" > + - const: "cpr_init_voltage2" > + - const: "cpr_init_voltage3" > + - const: "cpr_quotient1" > + - const: "cpr_quotient2" > + - const: "cpr_quotient3" > + - const: "cpr_ring_osc1" > + - const: "cpr_ring_osc2" > + - const: "cpr_ring_osc3" > + - const: "cpr_fuse_revision" > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-msm8998.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + operating-points-v2 = <&cpu_gold_opp_table>; > + power-domains = <&apc_cprh 0>; > + power-domain-names = "cprh"; > + }; > + > + cpu@100 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + operating-points-v2 = <&cpu_silver_opp_table>; > + power-domains = <&apc_cprh 1>; > + power-domain-names = "cprh"; > + }; > + }; > + > + cpu0_opp_table: opp-table-cpu0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-1843200000 { > + opp-hz = /bits/ 64 <1843200000>; > + required-opps = <&cprh_opp3>; > + }; > + > + opp-1094400000 { > + opp-hz = /bits/ 64 <1094400000>; > + required-opps = <&cprh_opp2>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cpu4_opp_table: opp-table-cpu4 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-2208000000 { > + opp-hz = /bits/ 64 <2208000000>; > + required-opps = <&cprh_opp3>; > + }; > + > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + required-opps = <&cprh_opp2>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cprh_opp_table: opp-table-cprh { > + compatible = "operating-points-v2-qcom-level"; > + > + cprh_opp1: opp-1 { > + opp-level = <1>; > + qcom,opp-fuse-level = <1>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + > + cprh_opp2: opp-2 { > + opp-level = <2>; > + qcom,opp-fuse-level = <2>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + > + cprh_opp3: opp-3 { > + opp-level = <3>; > + qcom,opp-fuse-level = <2 3>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + }; > + > + apc_cprh: power-controller@179c8000 { > + compatible = "qcom,msm8998-cprh", "qcom,cprh"; > + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; > + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; > + clock-names = "ref"; > + > + operating-points-v2 = <&cprh_opp_table>; > + #power-domain-cells = <1>; > + > + nvmem-cells = <&cpr_efuse_speedbin>, > + <&cpr_fuse_revision>, > + <&cpr_quot0_pwrcl>, > + <&cpr_quot1_pwrcl>, > + <&cpr_quot2_pwrcl>, > + <&cpr_quot3_pwrcl>, > + <&cpr_quot_offset1_pwrcl>, > + <&cpr_quot_offset2_pwrcl>, > + <&cpr_quot_offset3_pwrcl>, > + <&cpr_init_voltage0_pwrcl>, > + <&cpr_init_voltage1_pwrcl>, > + <&cpr_init_voltage2_pwrcl>, > + <&cpr_init_voltage3_pwrcl>, > + <&cpr_ro_sel0_pwrcl>, > + <&cpr_ro_sel1_pwrcl>, > + <&cpr_ro_sel2_pwrcl>, > + <&cpr_ro_sel3_pwrcl>, > + <&cpr_quot0_perfcl>, > + <&cpr_quot1_perfcl>, > + <&cpr_quot2_perfcl>, > + <&cpr_quot3_perfcl>, > + <&cpr_quot_offset1_perfcl>, > + <&cpr_quot_offset2_perfcl>, > + <&cpr_quot_offset3_perfcl>, > + <&cpr_init_voltage0_perfcl>, > + <&cpr_init_voltage1_perfcl>, > + <&cpr_init_voltage2_perfcl>, > + <&cpr_init_voltage3_perfcl>, > + <&cpr_ro_sel0_perfcl>, > + <&cpr_ro_sel1_perfcl>, > + <&cpr_ro_sel2_perfcl>, > + <&cpr_ro_sel3_perfcl>; > + nvmem-cell-names = "cpr_speed_bin", > + "cpr_fuse_revision", > + "cpr0_quotient1", > + "cpr0_quotient2", > + "cpr0_quotient3", > + "cpr0_quotient4", > + "cpr0_quotient_offset2", > + "cpr0_quotient_offset3", > + "cpr0_quotient_offset4", > + "cpr0_init_voltage1", > + "cpr0_init_voltage2", > + "cpr0_init_voltage3", > + "cpr0_init_voltage4", > + "cpr0_ring_osc1", > + "cpr0_ring_osc2", > + "cpr0_ring_osc3", > + "cpr0_ring_osc4", > + "cpr1_quotient1", > + "cpr1_quotient2", > + "cpr1_quotient3", > + "cpr1_quotient4", > + "cpr1_quotient_offset2", > + "cpr1_quotient_offset3", > + "cpr1_quotient_offset4", > + "cpr1_init_voltage1", > + "cpr1_init_voltage2", > + "cpr1_init_voltage3", > + "cpr1_init_voltage4", > + "cpr1_ring_osc1", > + "cpr1_ring_osc2", > + "cpr1_ring_osc3", > + "cpr1_ring_osc4"; > + }; > +... ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver 2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio 2023-01-16 9:43 ` Konrad Dybcio @ 2023-01-16 11:26 ` Konrad Dybcio 2023-01-16 16:36 ` Rob Herring 2 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 11:26 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, AngeloGioacchino Del Regno, Rob Herring, Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel On 16.01.2023 10:38, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Add the bindings for the CPR3 driver to the documentation. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > [Konrad: Make binding check pass; update AGdR's email] > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../bindings/soc/qcom/qcom,cpr3.yaml | 314 ++++++++++++++++++ > 1 file changed, 314 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > new file mode 100644 > index 000000000000..eb11af375e54 > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > @@ -0,0 +1,314 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#" > +$schema: "http://devicetree.org/meta-schemas/core.yaml#" > + > +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) > + > +description: | > + CPR (Core Power Reduction) is a technology to reduce core power on a CPU > + or other device. Each OPP of a device corresponds to a "corner" that has > + a range of valid voltages for a particular frequency. While the device is > + running at a particular frequency, CPR monitors dynamic factors such as > + temperature, etc. and suggests or, in the CPR-Hardened case performs, > + adjustments to the voltage to save power and meet silicon characteristic > + requirements. > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + > +properties: > + compatible: > + oneOf: > + - description: CPRv3 controller > + items: > + - const: qcom,cpr3 > + - description: CPRv4 controller > + items: > + - const: qcom,cpr4 > + - description: CPRv4-Hardened controller > + items: > + - enum: > + - qcom,msm8998-cprh > + - qcom,sdm630-cprh > + - const: qcom,cprh > + > + reg: > + description: Base address and size of the CPR controller(s) > + minItems: 1 > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + clock-names: > + items: > + - const: "ref" > + > + clocks: > + items: > + - description: CPR reference clock > + > + vdd-supply: > + description: Autonomous Phase Control (APC) or other power supply > + > + '#power-domain-cells': > + const: 1 > + > + acc-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to syscon for writing ACC settings > + > + nvmem-cells: > + description: Cells containing the fuse corners and revision data > + minItems: 10 > + maxItems: 32 > + > + nvmem-cell-names: > + minItems: 10 > + maxItems: 32 > + > + operating-points-v2: true > + > + power-domains: true > + > +required: > + - compatible > + - reg > + - clocks > + - clock-names > + - operating-points-v2 > + - "#power-domain-cells" > + - nvmem-cells > + - nvmem-cell-names > + > +additionalProperties: false > + > +allOf: > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,msm8998-cprh > + then: > + properties: > + nvmem-cell-names: > + items: > + - const: "cpr_speed_bin" > + - const: "cpr_fuse_revision" > + - const: "cpr0_quotient1" > + - const: "cpr0_quotient2" > + - const: "cpr0_quotient3" > + - const: "cpr0_quotient4" > + - const: "cpr0_quotient_offset2" > + - const: "cpr0_quotient_offset3" > + - const: "cpr0_quotient_offset4" > + - const: "cpr0_init_voltage1" > + - const: "cpr0_init_voltage2" > + - const: "cpr0_init_voltage3" > + - const: "cpr0_init_voltage4" > + - const: "cpr0_ring_osc1" > + - const: "cpr0_ring_osc2" > + - const: "cpr0_ring_osc3" > + - const: "cpr0_ring_osc4" > + - const: "cpr1_quotient1" > + - const: "cpr1_quotient2" > + - const: "cpr1_quotient3" > + - const: "cpr1_quotient4" > + - const: "cpr1_quotient_offset2" > + - const: "cpr1_quotient_offset3" > + - const: "cpr1_quotient_offset4" > + - const: "cpr1_init_voltage1" > + - const: "cpr1_init_voltage2" > + - const: "cpr1_init_voltage3" > + - const: "cpr1_init_voltage4" > + - const: "cpr1_ring_osc1" > + - const: "cpr1_ring_osc2" > + - const: "cpr1_ring_osc3" > + - const: "cpr1_ring_osc4" > + else: > + items: > + - const: "cpr_quotient_offset1" > + - const: "cpr_quotient_offset2" > + - const: "cpr_quotient_offset3" > + - const: "cpr_init_voltage1" > + - const: "cpr_init_voltage2" > + - const: "cpr_init_voltage3" > + - const: "cpr_quotient1" > + - const: "cpr_quotient2" > + - const: "cpr_quotient3" > + - const: "cpr_ring_osc1" > + - const: "cpr_ring_osc2" > + - const: "cpr_ring_osc3" > + - const: "cpr_fuse_revision" I suppose this block gotta go, as QCS404 CPR is not handled by this binding! Konrad > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-msm8998.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + operating-points-v2 = <&cpu_gold_opp_table>; > + power-domains = <&apc_cprh 0>; > + power-domain-names = "cprh"; > + }; > + > + cpu@100 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x100>; > + operating-points-v2 = <&cpu_silver_opp_table>; > + power-domains = <&apc_cprh 1>; > + power-domain-names = "cprh"; > + }; > + }; > + > + cpu0_opp_table: opp-table-cpu0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-1843200000 { > + opp-hz = /bits/ 64 <1843200000>; > + required-opps = <&cprh_opp3>; > + }; > + > + opp-1094400000 { > + opp-hz = /bits/ 64 <1094400000>; > + required-opps = <&cprh_opp2>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cpu4_opp_table: opp-table-cpu4 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-2208000000 { > + opp-hz = /bits/ 64 <2208000000>; > + required-opps = <&cprh_opp3>; > + }; > + > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + required-opps = <&cprh_opp2>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cprh_opp_table: opp-table-cprh { > + compatible = "operating-points-v2-qcom-level"; > + > + cprh_opp1: opp-1 { > + opp-level = <1>; > + qcom,opp-fuse-level = <1>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + > + cprh_opp2: opp-2 { > + opp-level = <2>; > + qcom,opp-fuse-level = <2>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + > + cprh_opp3: opp-3 { > + opp-level = <3>; > + qcom,opp-fuse-level = <2 3>; > + qcom,opp-cloop-vadj = <0>; > + qcom,opp-oloop-vadj = <0>; > + }; > + }; > + > + apc_cprh: power-controller@179c8000 { > + compatible = "qcom,msm8998-cprh", "qcom,cprh"; > + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; > + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; > + clock-names = "ref"; > + > + operating-points-v2 = <&cprh_opp_table>; > + #power-domain-cells = <1>; > + > + nvmem-cells = <&cpr_efuse_speedbin>, > + <&cpr_fuse_revision>, > + <&cpr_quot0_pwrcl>, > + <&cpr_quot1_pwrcl>, > + <&cpr_quot2_pwrcl>, > + <&cpr_quot3_pwrcl>, > + <&cpr_quot_offset1_pwrcl>, > + <&cpr_quot_offset2_pwrcl>, > + <&cpr_quot_offset3_pwrcl>, > + <&cpr_init_voltage0_pwrcl>, > + <&cpr_init_voltage1_pwrcl>, > + <&cpr_init_voltage2_pwrcl>, > + <&cpr_init_voltage3_pwrcl>, > + <&cpr_ro_sel0_pwrcl>, > + <&cpr_ro_sel1_pwrcl>, > + <&cpr_ro_sel2_pwrcl>, > + <&cpr_ro_sel3_pwrcl>, > + <&cpr_quot0_perfcl>, > + <&cpr_quot1_perfcl>, > + <&cpr_quot2_perfcl>, > + <&cpr_quot3_perfcl>, > + <&cpr_quot_offset1_perfcl>, > + <&cpr_quot_offset2_perfcl>, > + <&cpr_quot_offset3_perfcl>, > + <&cpr_init_voltage0_perfcl>, > + <&cpr_init_voltage1_perfcl>, > + <&cpr_init_voltage2_perfcl>, > + <&cpr_init_voltage3_perfcl>, > + <&cpr_ro_sel0_perfcl>, > + <&cpr_ro_sel1_perfcl>, > + <&cpr_ro_sel2_perfcl>, > + <&cpr_ro_sel3_perfcl>; > + nvmem-cell-names = "cpr_speed_bin", > + "cpr_fuse_revision", > + "cpr0_quotient1", > + "cpr0_quotient2", > + "cpr0_quotient3", > + "cpr0_quotient4", > + "cpr0_quotient_offset2", > + "cpr0_quotient_offset3", > + "cpr0_quotient_offset4", > + "cpr0_init_voltage1", > + "cpr0_init_voltage2", > + "cpr0_init_voltage3", > + "cpr0_init_voltage4", > + "cpr0_ring_osc1", > + "cpr0_ring_osc2", > + "cpr0_ring_osc3", > + "cpr0_ring_osc4", > + "cpr1_quotient1", > + "cpr1_quotient2", > + "cpr1_quotient3", > + "cpr1_quotient4", > + "cpr1_quotient_offset2", > + "cpr1_quotient_offset3", > + "cpr1_quotient_offset4", > + "cpr1_init_voltage1", > + "cpr1_init_voltage2", > + "cpr1_init_voltage3", > + "cpr1_init_voltage4", > + "cpr1_ring_osc1", > + "cpr1_ring_osc2", > + "cpr1_ring_osc3", > + "cpr1_ring_osc4"; > + }; > +... ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver 2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio 2023-01-16 9:43 ` Konrad Dybcio 2023-01-16 11:26 ` Konrad Dybcio @ 2023-01-16 16:36 ` Rob Herring 2023-01-16 17:03 ` Konrad Dybcio 2 siblings, 1 reply; 9+ messages in thread From: Rob Herring @ 2023-01-16 16:36 UTC (permalink / raw) To: Konrad Dybcio Cc: AngeloGioacchino Del Regno, AngeloGioacchino Del Regno, andersson, marijn.suijten, linux-arm-msm, devicetree, krzysztof.kozlowski, linux-kernel, Rob Herring, agross, Krzysztof Kozlowski On Mon, 16 Jan 2023 10:38:41 +0100, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Add the bindings for the CPR3 driver to the documentation. > > Reviewed-by: Rob Herring <robh@kernel.org> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > [Konrad: Make binding check pass; update AGdR's email] > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > .../bindings/soc/qcom/qcom,cpr3.yaml | 314 ++++++++++++++++++ > 1 file changed, 314 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-1: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-2: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-3: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-3:qcom,opp-fuse-level:0: [2, 3] is too long From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230116093845.72621-3-konrad.dybcio@linaro.org The base for the series is generally the latest rc1. A different dependency should be noted in *this* patch. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit after running the above command yourself. Note that DT_SCHEMA_FILES can be set to your schema file to speed up checking your schema. However, it must be unset to test all examples with your schema. ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver 2023-01-16 16:36 ` Rob Herring @ 2023-01-16 17:03 ` Konrad Dybcio 0 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 17:03 UTC (permalink / raw) To: Rob Herring Cc: AngeloGioacchino Del Regno, AngeloGioacchino Del Regno, andersson, marijn.suijten, linux-arm-msm, devicetree, krzysztof.kozlowski, linux-kernel, Rob Herring, agross, Krzysztof Kozlowski On 16.01.2023 17:36, Rob Herring wrote: > > On Mon, 16 Jan 2023 10:38:41 +0100, Konrad Dybcio wrote: >> From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> >> Add the bindings for the CPR3 driver to the documentation. >> >> Reviewed-by: Rob Herring <robh@kernel.org> >> Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> >> [Konrad: Make binding check pass; update AGdR's email] >> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> >> --- >> .../bindings/soc/qcom/qcom,cpr3.yaml | 314 ++++++++++++++++++ >> 1 file changed, 314 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml >> > > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' > on your patch (DT_CHECKER_FLAGS is new in v5.13): > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-1: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' > From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-2: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' > From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-3: 'qcom,opp-cloop-vadj', 'qcom,opp-oloop-vadj' do not match any of the regexes: 'pinctrl-[0-9]+' Argh, forgot to include that again.. My tree's so big it's hard to manage.. Hopefully the third time's the charm.. Konrad > From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.example.dtb: opp-table-cprh: opp-3:qcom,opp-fuse-level:0: [2, 3] is too long > From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > > doc reference errors (make refcheckdocs): > > See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230116093845.72621-3-konrad.dybcio@linaro.org > > The base for the series is generally the latest rc1. A different dependency > should be noted in *this* patch. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit after running the above command yourself. Note > that DT_SCHEMA_FILES can be set to your schema file to speed up checking > your schema. However, it must be unset to test all examples with your schema. > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array [not found] <20230116093845.72621-1-konrad.dybcio@linaro.org> 2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio @ 2023-01-16 9:38 ` Konrad Dybcio 2023-01-16 9:42 ` Viresh Kumar 2023-01-16 9:38 ` [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio 2 siblings, 1 reply; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 9:38 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, Konrad Dybcio, Rob Herring, Viresh Kumar, Nishanth Menon, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Niklas Cassel, linux-pm, devicetree, linux-kernel In some instances (particularly with CPRh) we might want to specifiy more than one qcom,opp-fuse-level, as the same OPP subnodes may be used by different "CPR threads". We need to make sure that n = num_threads entries is legal and so far nobody seems to use more than two, so let's allow that. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml index b9ce2e099ce9..a30ef93213c0 100644 --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml @@ -30,7 +30,9 @@ patternProperties: this OPP node. Sometimes several corners/levels shares a certain fuse corner/level. A fuse corner/level contains e.g. ref uV, min uV, and max uV. - $ref: /schemas/types.yaml#/definitions/uint32 + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 1 + maxItems: 2 required: - opp-level -- 2.39.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array 2023-01-16 9:38 ` [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio @ 2023-01-16 9:42 ` Viresh Kumar 0 siblings, 0 replies; 9+ messages in thread From: Viresh Kumar @ 2023-01-16 9:42 UTC (permalink / raw) To: Konrad Dybcio Cc: linux-arm-msm, andersson, agross, krzysztof.kozlowski, marijn.suijten, AngeloGioacchino Del Regno, Rob Herring, Viresh Kumar, Nishanth Menon, Stephen Boyd, Rob Herring, Krzysztof Kozlowski, Niklas Cassel, linux-pm, devicetree, linux-kernel On 16-01-23, 10:38, Konrad Dybcio wrote: > In some instances (particularly with CPRh) we might want to specifiy > more than one qcom,opp-fuse-level, as the same OPP subnodes may be > used by different "CPR threads". We need to make sure that > n = num_threads entries is legal and so far nobody seems to use more > than two, so let's allow that. > > Acked-by: Rob Herring <robh@kernel.org> > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- > Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > index b9ce2e099ce9..a30ef93213c0 100644 > --- a/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > +++ b/Documentation/devicetree/bindings/opp/opp-v2-qcom-level.yaml > @@ -30,7 +30,9 @@ patternProperties: > this OPP node. Sometimes several corners/levels shares a certain fuse > corner/level. A fuse corner/level contains e.g. ref uV, min uV, > and max uV. > - $ref: /schemas/types.yaml#/definitions/uint32 > + $ref: /schemas/types.yaml#/definitions/uint32-array > + minItems: 1 > + maxItems: 2 > > required: > - opp-level Applied. Thanks. -- viresh ^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh [not found] <20230116093845.72621-1-konrad.dybcio@linaro.org> 2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio 2023-01-16 9:38 ` [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio @ 2023-01-16 9:38 ` Konrad Dybcio 2023-01-16 14:30 ` Konrad Dybcio 2 siblings, 1 reply; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 9:38 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, Konrad Dybcio, AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> Now that the CPR v3/v4/Hardened is ready, enable it on MSM8998. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> [Konrad: separate from adding cpufreq, sort nodes and use lowercase hex] Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/msm8998.dtsi | 873 ++++++++++++++++++++++++++ 1 file changed, 873 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/msm8998.dtsi b/arch/arm64/boot/dts/qcom/msm8998.dtsi index af29a4bfd109..aa9b32ba2556 100644 --- a/arch/arm64/boot/dts/qcom/msm8998.dtsi +++ b/arch/arm64/boot/dts/qcom/msm8998.dtsi @@ -139,6 +139,9 @@ CPU0: cpu@0 { capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; L2_0: l2-cache { compatible = "cache"; cache-level = <2>; @@ -153,6 +156,9 @@ CPU1: cpu@1 { capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; }; CPU2: cpu@2 { @@ -163,6 +169,9 @@ CPU2: cpu@2 { capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; }; CPU3: cpu@3 { @@ -173,6 +182,9 @@ CPU3: cpu@3 { capacity-dmips-mhz = <1024>; cpu-idle-states = <&LITTLE_CPU_SLEEP_0 &LITTLE_CPU_SLEEP_1>; next-level-cache = <&L2_0>; + operating-points-v2 = <&cpu0_opp_table>; + power-domains = <&apc_cprh 0>; + power-domain-names = "cprh"; }; CPU4: cpu@100 { @@ -183,6 +195,9 @@ CPU4: cpu@100 { capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; L2_1: l2-cache { compatible = "cache"; cache-level = <2>; @@ -197,6 +212,9 @@ CPU5: cpu@101 { capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; }; CPU6: cpu@102 { @@ -207,6 +225,9 @@ CPU6: cpu@102 { capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; }; CPU7: cpu@103 { @@ -217,6 +238,9 @@ CPU7: cpu@103 { capacity-dmips-mhz = <1536>; cpu-idle-states = <&BIG_CPU_SLEEP_0 &BIG_CPU_SLEEP_1>; next-level-cache = <&L2_1>; + operating-points-v2 = <&cpu4_opp_table>; + power-domains = <&apc_cprh 1>; + power-domain-names = "cprh"; }; cpu-map { @@ -310,6 +334,606 @@ scm { }; }; + cprh_opp_table: opp-table-cprh { + compatible = "operating-points-v2-qcom-level"; + + cprh_opp1: opp-1 { + opp-level = <1>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp2: opp-2 { + opp-level = <2>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp3: opp-3 { + opp-level = <3>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp4: opp-4 { + opp-level = <4>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp5: opp-5 { + opp-level = <5>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp6: opp-6 { + opp-level = <6>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp7: opp-7 { + opp-level = <7>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp8: opp-8 { + opp-level = <8>; + qcom,opp-fuse-level = <1>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp9: opp-9 { + opp-level = <9>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp10: opp-10 { + opp-level = <10>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp11: opp-11 { + opp-level = <11>; + qcom,opp-fuse-level = <2>; + qcom,opp-cloop-vadj = <0>; + qcom,opp-oloop-vadj = <0>; + }; + + cprh_opp12: opp-12 { + opp-level = <12>; + qcom,opp-fuse-level = <3 2>; + qcom,opp-cloop-vadj = <(-10000) (-10000)>; + qcom,opp-oloop-vadj = <(-12000) (-8000)>; + }; + + cprh_opp13: opp-13 { + opp-level = <13>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-11000) (-10000)>; + qcom,opp-oloop-vadj = <(-16000) (-16000)>; + }; + + cprh_opp14: opp-14 { + opp-level = <14>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-12000) (-11000)>; + qcom,opp-oloop-vadj = <(-16000) (-12000)>; + }; + + cprh_opp15: opp-15 { + opp-level = <15>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-13000) (-12000)>; + qcom,opp-oloop-vadj = <(-12000) (-16000)>; + }; + + cprh_opp16: opp-16 { + opp-level = <16>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-14000) (-12000)>; + qcom,opp-oloop-vadj = <(-12000) (-16000)>; + }; + + cprh_opp17: opp-17 { + opp-level = <17>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-14000) (-13000)>; + qcom,opp-oloop-vadj = <(-16000) (-12000)>; + }; + + cprh_opp18: opp-18 { + opp-level = <18>; + qcom,opp-fuse-level = <3>; + qcom,opp-cloop-vadj = <(-15000) (-14000)>; + qcom,opp-oloop-vadj = <(-16000) (-16000)>; + }; + + cprh_opp19: opp-19 { + opp-level = <19>; + qcom,opp-fuse-level = <4 3>; + qcom,opp-cloop-vadj = <(-21000) (-14000)>; + qcom,opp-oloop-vadj = <(-20000) (-16000)>; + }; + + cprh_opp20: opp-20 { + opp-level = <20>; + qcom,opp-fuse-level = <4 3>; + qcom,opp-cloop-vadj = <(-24000) (-15000)>; + qcom,opp-oloop-vadj = <(-24000) (-16000)>; + }; + + cprh_opp21: opp-21 { + opp-level = <21>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <(-26000) (-16000)>; + qcom,opp-oloop-vadj = <(-28000) (-24000)>; + }; + + cprh_opp22: opp-22 { + opp-level = <22>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <(-28000) (-16000)>; + qcom,opp-oloop-vadj = <(-28000) (-16000)>; + }; + + cprh_opp23: opp-23 { + opp-level = <23>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-17000)>; + qcom,opp-oloop-vadj = <0 (-20000)>; + }; + + cprh_opp24: opp-24 { + opp-level = <24>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-15000)>; + qcom,opp-oloop-vadj = <0 (-16000)>; + }; + + cprh_opp25: opp-25 { + opp-level = <25>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-14000)>; + qcom,opp-oloop-vadj = <0 (-12000)>; + }; + + cprh_opp26: opp-26 { + opp-level = <26>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-27000)>; + qcom,opp-oloop-vadj = <0 (-28000)>; + }; + + cprh_opp27: opp-27 { + opp-level = <27>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-27000)>; + qcom,opp-oloop-vadj = <0 (-28000)>; + }; + + cprh_opp28: opp-28 { + opp-level = <28>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-28000)>; + qcom,opp-oloop-vadj = <0 (-28000)>; + }; + + cprh_opp29: opp-29 { + opp-level = <29>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-28000)>; + qcom,opp-oloop-vadj = <0 (-28000)>; + }; + + cprh_opp30: opp-30 { + opp-level = <30>; + qcom,opp-fuse-level = <4>; + qcom,opp-cloop-vadj = <0 (-28000)>; + qcom,opp-oloop-vadj = <0 (-28000)>; + }; + }; + + cpu0_opp_table: opp-table-cpu0 { + compatible = "operating-points-v2"; + opp-shared; + + opp-1900800000 { + opp-hz = /bits/ 64 <1900800000>; + required-opps = <&cprh_opp22>; + qcom,pll-override = <0x094f004f>; + qcom,spare-data = <3>; + }; + + opp-1824000000 { + opp-hz = /bits/ 64 <1824000000>; + required-opps = <&cprh_opp21>; + qcom,pll-override = <0x084c004c>; + qcom,spare-data = <3>; + }; + + opp-1747200000 { + opp-hz = /bits/ 64 <1747200000>; + required-opps = <&cprh_opp20>; + qcom,pll-override = <0x08490049>; + qcom,spare-data = <2>; + }; + + opp-1670400000 { + opp-hz = /bits/ 64 <1670400000>; + required-opps = <&cprh_opp19>; + qcom,pll-override = <0x08460046>; + qcom,spare-data = <2>; + }; + + opp-1555200000 { + opp-hz = /bits/ 64 <1555200000>; + required-opps = <&cprh_opp18>; + qcom,pll-override = <0x07410041>; + qcom,spare-data = <2>; + }; + + opp-1478400000 { + opp-hz = /bits/ 64 <1478400000>; + required-opps = <&cprh_opp17>; + qcom,pll-override = <0x073e003e>; + qcom,spare-data = <2>; + }; + + opp-1401600000 { + opp-hz = /bits/ 64 <1401600000>; + required-opps = <&cprh_opp16>; + qcom,pll-override = <0x063a003a>; + qcom,spare-data = <2>; + }; + + opp-1324800000 { + opp-hz = /bits/ 64 <1324800000>; + required-opps = <&cprh_opp15>; + qcom,pll-override = <0x06370037>; + qcom,spare-data = <2>; + }; + + opp-1248000000 { + opp-hz = /bits/ 64 <1248000000>; + required-opps = <&cprh_opp14>; + qcom,pll-override = <0x05340034>; + qcom,spare-data = <2>; + }; + + opp-1171200000 { + opp-hz = /bits/ 64 <1171200000>; + required-opps = <&cprh_opp13>; + qcom,pll-override = <0x05310031>; + qcom,spare-data = <2>; + }; + + opp-1094400000 { + opp-hz = /bits/ 64 <1094400000>; + required-opps = <&cprh_opp12>; + qcom,pll-override = <0x052e002e>; + qcom,spare-data = <2>; + }; + + opp-1036800000 { + opp-hz = /bits/ 64 <1036800000>; + required-opps = <&cprh_opp11>; + qcom,pll-override = <0x042b002b>; + qcom,spare-data = <1>; + }; + + opp-960000000 { + opp-hz = /bits/ 64 <960000000>; + required-opps = <&cprh_opp10>; + qcom,pll-override = <0x4280028>; + qcom,spare-data = <1>; + }; + + opp-883200000 { + opp-hz = /bits/ 64 <883200000>; + required-opps = <&cprh_opp9>; + qcom,pll-override = <0x4250025>; + qcom,spare-data = <1>; + }; + + opp-825600000 { + opp-hz = /bits/ 64 <825600000>; + required-opps = <&cprh_opp8>; + qcom,pll-override = <0x3200022>; + qcom,spare-data = <1>; + }; + + opp-748800000 { + opp-hz = /bits/ 64 <748800000>; + required-opps = <&cprh_opp7>; + qcom,pll-override = <0x3200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-672000000 { + opp-hz = /bits/ 64 <672000000>; + required-opps = <&cprh_opp6>; + qcom,pll-override = <0x3200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-595200000 { + opp-hz = /bits/ 64 <595200000>; + required-opps = <&cprh_opp5>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-518400000 { + opp-hz = /bits/ 64 <518400000>; + required-opps = <&cprh_opp4>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-441600000 { + opp-hz = /bits/ 64 <441600000>; + required-opps = <&cprh_opp3>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-364800000 { + opp-hz = /bits/ 64 <364800000>; + required-opps = <&cprh_opp2>; + qcom,pll-override = <0x1200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + qcom,pll-override = <0x1200020>; + }; + }; + + cpu4_opp_table: opp-table-cpu4 { + compatible = "operating-points-v2"; + opp-shared; + + opp-2361600000 { + opp-hz = /bits/ 64 <2361600000>; + required-opps = <&cprh_opp30>; + qcom,pll-override = <0x0a620062>; + qcom,spare-data = <3>; + }; + + opp-2342400000 { + opp-hz = /bits/ 64 <2342400000>; + required-opps = <&cprh_opp29>; + qcom,pll-override = <0x0a620062>; + qcom,spare-data = <3>; + }; + + opp-2323200000 { + opp-hz = /bits/ 64 <2323200000>; + required-opps = <&cprh_opp28>; + qcom,pll-override = <0x0a610061>; + qcom,spare-data = <3>; + }; + + opp-2265600000 { + opp-hz = /bits/ 64 <2265600000>; + required-opps = <&cprh_opp27>; + qcom,pll-override = <0x0a5e005e>; + qcom,spare-data = <3>; + }; + + opp-2208000000 { + opp-hz = /bits/ 64 <2208000000>; + required-opps = <&cprh_opp26>; + qcom,pll-override = <0x0a5c005c>; + qcom,spare-data = <3>; + }; + + opp-2112000000 { + opp-hz = /bits/ 64 <2112000000>; + required-opps = <&cprh_opp25>; + qcom,pll-override = <0x0a580058>; + qcom,spare-data = <3>; + }; + + opp-2035200000 { + opp-hz = /bits/ 64 <2035200000>; + required-opps = <&cprh_opp24>; + qcom,pll-override = <0x09550055>; + qcom,spare-data = <3>; + }; + + opp-1958400000 { + opp-hz = /bits/ 64 <1958400000>; + required-opps = <&cprh_opp23>; + qcom,pll-override = <0x09520052>; + qcom,spare-data = <2>; + }; + + opp-1881600000 { + opp-hz = /bits/ 64 <1881600000>; + required-opps = <&cprh_opp22>; + qcom,pll-override = <0x094e004e>; + qcom,spare-data = <2>; + }; + + opp-1804800000 { + opp-hz = /bits/ 64 <1804800000>; + required-opps = <&cprh_opp21>; + qcom,pll-override = <0x084b004b>; + qcom,spare-data = <2>; + }; + + opp-1728000000 { + opp-hz = /bits/ 64 <1728000000>; + required-opps = <&cprh_opp20>; + qcom,pll-override = <0x08480048>; + qcom,spare-data = <2>; + }; + + opp-1651200000 { + opp-hz = /bits/ 64 <1651200000>; + required-opps = <&cprh_opp19>; + qcom,pll-override = <0x07450045>; + qcom,spare-data = <2>; + }; + + opp-1574400000 { + opp-hz = /bits/ 64 <1574400000>; + required-opps = <&cprh_opp18>; + qcom,pll-override = <0x07420042>; + qcom,spare-data = <2>; + }; + + opp-1497600000 { + opp-hz = /bits/ 64 <1497600000>; + required-opps = <&cprh_opp17>; + qcom,pll-override = <0x073e003e>; + qcom,spare-data = <2>; + }; + + opp-1420800000 { + opp-hz = /bits/ 64 <1420800000>; + required-opps = <&cprh_opp16>; + qcom,pll-override = <0x063b003b>; + qcom,spare-data = <2>; + }; + + opp-1344000000 { + opp-hz = /bits/ 64 <1344000000>; + required-opps = <&cprh_opp15>; + qcom,pll-override = <0x06380038>; + qcom,spare-data = <2>; + }; + + opp-1267200000 { + opp-hz = /bits/ 64 <1267200000>; + required-opps = <&cprh_opp14>; + qcom,pll-override = <0x06350035>; + qcom,spare-data = <2>; + }; + + opp-1190400000 { + opp-hz = /bits/ 64 <1190400000>; + required-opps = <&cprh_opp13>; + qcom,pll-override = <0x05320032>; + qcom,spare-data = <2>; + }; + + opp-1132800000 { + opp-hz = /bits/ 64 <1132800000>; + required-opps = <&cprh_opp12>; + qcom,pll-override = <0x052f002f>; + qcom,spare-data = <1>; + }; + + opp-1056000000 { + opp-hz = /bits/ 64 <1056000000>; + required-opps = <&cprh_opp11>; + qcom,pll-override = <0x052c002c>; + qcom,spare-data = <1>; + }; + + opp-979200000 { + opp-hz = /bits/ 64 <979200000>; + required-opps = <&cprh_opp10>; + qcom,pll-override = <0x4290029>; + qcom,spare-data = <1>; + }; + + opp-902400000 { + opp-hz = /bits/ 64 <902400000>; + required-opps = <&cprh_opp9>; + qcom,pll-override = <0x4260026>; + qcom,spare-data = <1>; + }; + + opp-806400000 { + opp-hz = /bits/ 64 <806400000>; + required-opps = <&cprh_opp8>; + qcom,pll-override = <0x3200022>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-729600000 { + opp-hz = /bits/ 64 <729600000>; + required-opps = <&cprh_opp7>; + qcom,pll-override = <0x3200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-652800000 { + opp-hz = /bits/ 64 <652800000>; + required-opps = <&cprh_opp6>; + qcom,pll-override = <0x3200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-576000000 { + opp-hz = /bits/ 64 <576000000>; + required-opps = <&cprh_opp5>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-499200000 { + opp-hz = /bits/ 64 <499200000>; + required-opps = <&cprh_opp4>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-422400000 { + opp-hz = /bits/ 64 <422400000>; + required-opps = <&cprh_opp3>; + qcom,pll-override = <0x2200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-345600000 { + opp-hz = /bits/ 64 <345600000>; + required-opps = <&cprh_opp2>; + qcom,pll-override = <0x1200020>; + qcom,spare-data = <1>; + qcom,pll-div = <1>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&cprh_opp1>; + qcom,pll-override = <0x1200020>; + qcom,spare-data = <1>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -839,6 +1463,174 @@ qfprom: qfprom@784000 { #address-cells = <1>; #size-cells = <1>; + cpr_efuse_speedbin: speedbin@133 { + reg = <0x133 0x8>; + bits = <5 3>; + }; + + cpr_fuse_revision: cpr_fusing_rev@13e { + reg = <0x13e 0x1>; + bits = <3 3>; + }; + + /* CPR Ring Oscillator: Power Cluster */ + cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 { + reg = <0x218 0x1>; + bits = <0 4>; + }; + + cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 { + reg = <0x218 0x1>; + bits = <4 4>; + }; + + cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 { + reg = <0x219 0x1>; + bits = <0 4>; + }; + + cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 { + reg = <0x219 0x1>; + bits = <4 4>; + }; + + /* CPR Init Voltage: Power Cluster */ + cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a { + reg = <0x21a 0x1>; + bits = <0 6>; + }; + + cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a { + reg = <0x21a 0x1>; + bits = <6 6>; + }; + + cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b { + reg = <0x21b 0x1>; + bits = <4 6>; + }; + + cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c { + reg = <0x21c 0x1>; + bits = <2 6>; + }; + + /* CPR Target Quotients: Power Cluster */ + cpr_quot3_pwrcl: quot3_pwrcl@21d { + reg = <0x21d 0x2>; + bits = <6 12>; + }; + + cpr_quot2_pwrcl: quot2_pwrcl@21f { + reg = <0x21f 0x2>; + bits = <2 11>; + }; + + cpr_quot1_pwrcl: quot1_pwrcl@220 { + reg = <0x220 0x2>; + bits = <6 12>; + }; + + cpr_quot0_pwrcl: quot0_pwrcl@222 { + reg = <0x222 0x2>; + bits = <2 12>; + }; + + /* CPR Quotient Offsets: Power Cluster */ + cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 { + reg = <0x226 0x1>; + bits = <1 7>; + }; + + cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 { + reg = <0x227 0x1>; + bits = <0 7>; + }; + + cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 { + reg = <0x227 0x1>; + bits = <7 6>; + }; + + /* CPR Ring Oscillator: Performance Cluster */ + cpr_ro_sel3_perfcl: rosel3_perfcl@229 { + reg = <0x229 0x1>; + bits = <6 4>; + }; + + cpr_ro_sel2_perfcl: rosel2_perfcl@22a { + reg = <0x22a 0x1>; + bits = <2 4>; + }; + + cpr_ro_sel1_perfcl: rosel1_perfcl@22a { + reg = <0x22a 0x1>; + bits = <6 4>; + }; + + cpr_ro_sel0_perfcl: rosel0_perfcl@22b { + reg = <0x22b 0x1>; + bits = <2 4>; + }; + + /* CPR Init Voltage: Performance Cluster */ + cpr_init_voltage3_perfcl: ivolt3_perfcl@22b { + reg = <0x22b 0x1>; + bits = <6 6>; + }; + + cpr_init_voltage2_perfcl: ivolt2_perfcl@22c { + reg = <0x22c 0x1>; + bits = <4 6>; + }; + + cpr_init_voltage1_perfcl: ivolt1_perfcl@22d { + reg = <0x22d 0x1>; + bits = <2 6>; + }; + + cpr_init_voltage0_perfcl: ivolt0_perfcl@22e { + reg = <0x22e 0x1>; + bits = <0 6>; + }; + + /* CPR Target Quotients: Performance Cluster */ + cpr_quot3_perfcl: quot3_perfcl@22f { + reg = <0x22f 0x2>; + bits = <4 11>; + }; + + cpr_quot2_perfcl: quot2_perfcl@231 { + reg = <0x231 0x2>; + bits = <0 12>; + }; + + cpr_quot1_perfcl: quot1_perfcl@232 { + reg = <0x232 0x2>; + bits = <4 12>; + }; + + cpr_quot0_perfcl: quot0_perfcl@234 { + reg = <0x234 0x2>; + bits = <0 12>; + }; + + /* CPR Quotient Offsets: Performance Cluster */ + cpr_quot_offset3_perfcl: qoff3_perfcl@237 { + reg = <0x237 0x1>; + bits = <7 6>; + }; + + cpr_quot_offset2_perfcl: qoff2_perfcl@238 { + reg = <0x238 0x1>; + bits = <6 7>; + }; + + cpr_quot_offset1_perfcl: qoff1_perfcl@239 { + reg = <0x239 0x1>; + bits = <5 3>; + }; + qusb2_hstx_trim: hstx-trim@23a { reg = <0x23a 0x1>; bits = <0 4>; @@ -2998,6 +3790,87 @@ frame@17928000 { }; }; + apc_cprh: power-controller@179c8000 { + compatible = "qcom,msm8998-cprh", "qcom,cprh"; + reg = <0x179c8000 0x4000>, <0x179c4000 0x4000>; + + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + clock-names = "ref"; + + /* Set the CPR clock here, it needs to match XO */ + assigned-clocks = <&gcc GCC_HMSS_RBCPR_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&cprh_opp_table>; + power-domains = <&rpmpd MSM8998_VDDCX_AO>; + #power-domain-cells = <1>; + + nvmem-cells = <&cpr_efuse_speedbin>, + <&cpr_fuse_revision>, + <&cpr_quot0_pwrcl>, + <&cpr_quot1_pwrcl>, + <&cpr_quot2_pwrcl>, + <&cpr_quot3_pwrcl>, + <&cpr_quot_offset1_pwrcl>, + <&cpr_quot_offset2_pwrcl>, + <&cpr_quot_offset3_pwrcl>, + <&cpr_init_voltage0_pwrcl>, + <&cpr_init_voltage1_pwrcl>, + <&cpr_init_voltage2_pwrcl>, + <&cpr_init_voltage3_pwrcl>, + <&cpr_ro_sel0_pwrcl>, + <&cpr_ro_sel1_pwrcl>, + <&cpr_ro_sel2_pwrcl>, + <&cpr_ro_sel3_pwrcl>, + <&cpr_quot0_perfcl>, + <&cpr_quot1_perfcl>, + <&cpr_quot2_perfcl>, + <&cpr_quot3_perfcl>, + <&cpr_quot_offset1_perfcl>, + <&cpr_quot_offset2_perfcl>, + <&cpr_quot_offset3_perfcl>, + <&cpr_init_voltage0_perfcl>, + <&cpr_init_voltage1_perfcl>, + <&cpr_init_voltage2_perfcl>, + <&cpr_init_voltage3_perfcl>, + <&cpr_ro_sel0_perfcl>, + <&cpr_ro_sel1_perfcl>, + <&cpr_ro_sel2_perfcl>, + <&cpr_ro_sel3_perfcl>; + nvmem-cell-names = "cpr_speed_bin", + "cpr_fuse_revision", + "cpr0_quotient1", + "cpr0_quotient2", + "cpr0_quotient3", + "cpr0_quotient4", + "cpr0_quotient_offset2", + "cpr0_quotient_offset3", + "cpr0_quotient_offset4", + "cpr0_init_voltage1", + "cpr0_init_voltage2", + "cpr0_init_voltage3", + "cpr0_init_voltage4", + "cpr0_ring_osc1", + "cpr0_ring_osc2", + "cpr0_ring_osc3", + "cpr0_ring_osc4", + "cpr1_quotient1", + "cpr1_quotient2", + "cpr1_quotient3", + "cpr1_quotient4", + "cpr1_quotient_offset2", + "cpr1_quotient_offset3", + "cpr1_quotient_offset4", + "cpr1_init_voltage1", + "cpr1_init_voltage2", + "cpr1_init_voltage3", + "cpr1_init_voltage4", + "cpr1_ring_osc1", + "cpr1_ring_osc2", + "cpr1_ring_osc3", + "cpr1_ring_osc4"; + }; + intc: interrupt-controller@17a00000 { compatible = "arm,gic-v3"; reg = <0x17a00000 0x10000>, /* GICD */ -- 2.39.0 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh 2023-01-16 9:38 ` [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio @ 2023-01-16 14:30 ` Konrad Dybcio 0 siblings, 0 replies; 9+ messages in thread From: Konrad Dybcio @ 2023-01-16 14:30 UTC (permalink / raw) To: linux-arm-msm, andersson, agross, krzysztof.kozlowski Cc: marijn.suijten, AngeloGioacchino Del Regno, AngeloGioacchino Del Regno, Rob Herring, Krzysztof Kozlowski, devicetree, linux-kernel On 16.01.2023 10:38, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > > Now that the CPR v3/v4/Hardened is ready, enable it on MSM8998. > > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org> > [Konrad: separate from adding cpufreq, sort nodes and use lowercase hex] > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> > --- [...] > + cpu0_opp_table: opp-table-cpu0 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-1900800000 { > + opp-hz = /bits/ 64 <1900800000>; > + required-opps = <&cprh_opp22>; > + qcom,pll-override = <0x094f004f>; > + qcom,spare-data = <3>; As Dmitry pointed out to me in private, these properties belong to the CPUFREQ patch and - with this series alone - are considered undocumented. Konrad > + }; > + > + opp-1824000000 { > + opp-hz = /bits/ 64 <1824000000>; > + required-opps = <&cprh_opp21>; > + qcom,pll-override = <0x084c004c>; > + qcom,spare-data = <3>; > + }; > + > + opp-1747200000 { > + opp-hz = /bits/ 64 <1747200000>; > + required-opps = <&cprh_opp20>; > + qcom,pll-override = <0x08490049>; > + qcom,spare-data = <2>; > + }; > + > + opp-1670400000 { > + opp-hz = /bits/ 64 <1670400000>; > + required-opps = <&cprh_opp19>; > + qcom,pll-override = <0x08460046>; > + qcom,spare-data = <2>; > + }; > + > + opp-1555200000 { > + opp-hz = /bits/ 64 <1555200000>; > + required-opps = <&cprh_opp18>; > + qcom,pll-override = <0x07410041>; > + qcom,spare-data = <2>; > + }; > + > + opp-1478400000 { > + opp-hz = /bits/ 64 <1478400000>; > + required-opps = <&cprh_opp17>; > + qcom,pll-override = <0x073e003e>; > + qcom,spare-data = <2>; > + }; > + > + opp-1401600000 { > + opp-hz = /bits/ 64 <1401600000>; > + required-opps = <&cprh_opp16>; > + qcom,pll-override = <0x063a003a>; > + qcom,spare-data = <2>; > + }; > + > + opp-1324800000 { > + opp-hz = /bits/ 64 <1324800000>; > + required-opps = <&cprh_opp15>; > + qcom,pll-override = <0x06370037>; > + qcom,spare-data = <2>; > + }; > + > + opp-1248000000 { > + opp-hz = /bits/ 64 <1248000000>; > + required-opps = <&cprh_opp14>; > + qcom,pll-override = <0x05340034>; > + qcom,spare-data = <2>; > + }; > + > + opp-1171200000 { > + opp-hz = /bits/ 64 <1171200000>; > + required-opps = <&cprh_opp13>; > + qcom,pll-override = <0x05310031>; > + qcom,spare-data = <2>; > + }; > + > + opp-1094400000 { > + opp-hz = /bits/ 64 <1094400000>; > + required-opps = <&cprh_opp12>; > + qcom,pll-override = <0x052e002e>; > + qcom,spare-data = <2>; > + }; > + > + opp-1036800000 { > + opp-hz = /bits/ 64 <1036800000>; > + required-opps = <&cprh_opp11>; > + qcom,pll-override = <0x042b002b>; > + qcom,spare-data = <1>; > + }; > + > + opp-960000000 { > + opp-hz = /bits/ 64 <960000000>; > + required-opps = <&cprh_opp10>; > + qcom,pll-override = <0x4280028>; > + qcom,spare-data = <1>; > + }; > + > + opp-883200000 { > + opp-hz = /bits/ 64 <883200000>; > + required-opps = <&cprh_opp9>; > + qcom,pll-override = <0x4250025>; > + qcom,spare-data = <1>; > + }; > + > + opp-825600000 { > + opp-hz = /bits/ 64 <825600000>; > + required-opps = <&cprh_opp8>; > + qcom,pll-override = <0x3200022>; > + qcom,spare-data = <1>; > + }; > + > + opp-748800000 { > + opp-hz = /bits/ 64 <748800000>; > + required-opps = <&cprh_opp7>; > + qcom,pll-override = <0x3200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-672000000 { > + opp-hz = /bits/ 64 <672000000>; > + required-opps = <&cprh_opp6>; > + qcom,pll-override = <0x3200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-595200000 { > + opp-hz = /bits/ 64 <595200000>; > + required-opps = <&cprh_opp5>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-518400000 { > + opp-hz = /bits/ 64 <518400000>; > + required-opps = <&cprh_opp4>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-441600000 { > + opp-hz = /bits/ 64 <441600000>; > + required-opps = <&cprh_opp3>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-364800000 { > + opp-hz = /bits/ 64 <364800000>; > + required-opps = <&cprh_opp2>; > + qcom,pll-override = <0x1200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + qcom,pll-override = <0x1200020>; > + }; > + }; > + > + cpu4_opp_table: opp-table-cpu4 { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-2361600000 { > + opp-hz = /bits/ 64 <2361600000>; > + required-opps = <&cprh_opp30>; > + qcom,pll-override = <0x0a620062>; > + qcom,spare-data = <3>; > + }; > + > + opp-2342400000 { > + opp-hz = /bits/ 64 <2342400000>; > + required-opps = <&cprh_opp29>; > + qcom,pll-override = <0x0a620062>; > + qcom,spare-data = <3>; > + }; > + > + opp-2323200000 { > + opp-hz = /bits/ 64 <2323200000>; > + required-opps = <&cprh_opp28>; > + qcom,pll-override = <0x0a610061>; > + qcom,spare-data = <3>; > + }; > + > + opp-2265600000 { > + opp-hz = /bits/ 64 <2265600000>; > + required-opps = <&cprh_opp27>; > + qcom,pll-override = <0x0a5e005e>; > + qcom,spare-data = <3>; > + }; > + > + opp-2208000000 { > + opp-hz = /bits/ 64 <2208000000>; > + required-opps = <&cprh_opp26>; > + qcom,pll-override = <0x0a5c005c>; > + qcom,spare-data = <3>; > + }; > + > + opp-2112000000 { > + opp-hz = /bits/ 64 <2112000000>; > + required-opps = <&cprh_opp25>; > + qcom,pll-override = <0x0a580058>; > + qcom,spare-data = <3>; > + }; > + > + opp-2035200000 { > + opp-hz = /bits/ 64 <2035200000>; > + required-opps = <&cprh_opp24>; > + qcom,pll-override = <0x09550055>; > + qcom,spare-data = <3>; > + }; > + > + opp-1958400000 { > + opp-hz = /bits/ 64 <1958400000>; > + required-opps = <&cprh_opp23>; > + qcom,pll-override = <0x09520052>; > + qcom,spare-data = <2>; > + }; > + > + opp-1881600000 { > + opp-hz = /bits/ 64 <1881600000>; > + required-opps = <&cprh_opp22>; > + qcom,pll-override = <0x094e004e>; > + qcom,spare-data = <2>; > + }; > + > + opp-1804800000 { > + opp-hz = /bits/ 64 <1804800000>; > + required-opps = <&cprh_opp21>; > + qcom,pll-override = <0x084b004b>; > + qcom,spare-data = <2>; > + }; > + > + opp-1728000000 { > + opp-hz = /bits/ 64 <1728000000>; > + required-opps = <&cprh_opp20>; > + qcom,pll-override = <0x08480048>; > + qcom,spare-data = <2>; > + }; > + > + opp-1651200000 { > + opp-hz = /bits/ 64 <1651200000>; > + required-opps = <&cprh_opp19>; > + qcom,pll-override = <0x07450045>; > + qcom,spare-data = <2>; > + }; > + > + opp-1574400000 { > + opp-hz = /bits/ 64 <1574400000>; > + required-opps = <&cprh_opp18>; > + qcom,pll-override = <0x07420042>; > + qcom,spare-data = <2>; > + }; > + > + opp-1497600000 { > + opp-hz = /bits/ 64 <1497600000>; > + required-opps = <&cprh_opp17>; > + qcom,pll-override = <0x073e003e>; > + qcom,spare-data = <2>; > + }; > + > + opp-1420800000 { > + opp-hz = /bits/ 64 <1420800000>; > + required-opps = <&cprh_opp16>; > + qcom,pll-override = <0x063b003b>; > + qcom,spare-data = <2>; > + }; > + > + opp-1344000000 { > + opp-hz = /bits/ 64 <1344000000>; > + required-opps = <&cprh_opp15>; > + qcom,pll-override = <0x06380038>; > + qcom,spare-data = <2>; > + }; > + > + opp-1267200000 { > + opp-hz = /bits/ 64 <1267200000>; > + required-opps = <&cprh_opp14>; > + qcom,pll-override = <0x06350035>; > + qcom,spare-data = <2>; > + }; > + > + opp-1190400000 { > + opp-hz = /bits/ 64 <1190400000>; > + required-opps = <&cprh_opp13>; > + qcom,pll-override = <0x05320032>; > + qcom,spare-data = <2>; > + }; > + > + opp-1132800000 { > + opp-hz = /bits/ 64 <1132800000>; > + required-opps = <&cprh_opp12>; > + qcom,pll-override = <0x052f002f>; > + qcom,spare-data = <1>; > + }; > + > + opp-1056000000 { > + opp-hz = /bits/ 64 <1056000000>; > + required-opps = <&cprh_opp11>; > + qcom,pll-override = <0x052c002c>; > + qcom,spare-data = <1>; > + }; > + > + opp-979200000 { > + opp-hz = /bits/ 64 <979200000>; > + required-opps = <&cprh_opp10>; > + qcom,pll-override = <0x4290029>; > + qcom,spare-data = <1>; > + }; > + > + opp-902400000 { > + opp-hz = /bits/ 64 <902400000>; > + required-opps = <&cprh_opp9>; > + qcom,pll-override = <0x4260026>; > + qcom,spare-data = <1>; > + }; > + > + opp-806400000 { > + opp-hz = /bits/ 64 <806400000>; > + required-opps = <&cprh_opp8>; > + qcom,pll-override = <0x3200022>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-729600000 { > + opp-hz = /bits/ 64 <729600000>; > + required-opps = <&cprh_opp7>; > + qcom,pll-override = <0x3200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-652800000 { > + opp-hz = /bits/ 64 <652800000>; > + required-opps = <&cprh_opp6>; > + qcom,pll-override = <0x3200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-576000000 { > + opp-hz = /bits/ 64 <576000000>; > + required-opps = <&cprh_opp5>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-499200000 { > + opp-hz = /bits/ 64 <499200000>; > + required-opps = <&cprh_opp4>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-422400000 { > + opp-hz = /bits/ 64 <422400000>; > + required-opps = <&cprh_opp3>; > + qcom,pll-override = <0x2200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-345600000 { > + opp-hz = /bits/ 64 <345600000>; > + required-opps = <&cprh_opp2>; > + qcom,pll-override = <0x1200020>; > + qcom,spare-data = <1>; > + qcom,pll-div = <1>; > + }; > + > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + qcom,pll-override = <0x1200020>; > + qcom,spare-data = <1>; > + }; > + }; > + > psci { > compatible = "arm,psci-1.0"; > method = "smc"; > @@ -839,6 +1463,174 @@ qfprom: qfprom@784000 { > #address-cells = <1>; > #size-cells = <1>; > > + cpr_efuse_speedbin: speedbin@133 { > + reg = <0x133 0x8>; > + bits = <5 3>; > + }; > + > + cpr_fuse_revision: cpr_fusing_rev@13e { > + reg = <0x13e 0x1>; > + bits = <3 3>; > + }; > + > + /* CPR Ring Oscillator: Power Cluster */ > + cpr_ro_sel3_pwrcl: rosel3_pwrcl@218 { > + reg = <0x218 0x1>; > + bits = <0 4>; > + }; > + > + cpr_ro_sel2_pwrcl: rosel2_pwrcl@218 { > + reg = <0x218 0x1>; > + bits = <4 4>; > + }; > + > + cpr_ro_sel1_pwrcl: rosel1_pwrcl@219 { > + reg = <0x219 0x1>; > + bits = <0 4>; > + }; > + > + cpr_ro_sel0_pwrcl: rosel0_pwrcl@219 { > + reg = <0x219 0x1>; > + bits = <4 4>; > + }; > + > + /* CPR Init Voltage: Power Cluster */ > + cpr_init_voltage3_pwrcl: ivolt3_pwrcl@21a { > + reg = <0x21a 0x1>; > + bits = <0 6>; > + }; > + > + cpr_init_voltage2_pwrcl: ivolt2_pwrcl@21a { > + reg = <0x21a 0x1>; > + bits = <6 6>; > + }; > + > + cpr_init_voltage1_pwrcl: ivolt1_pwrcl@21b { > + reg = <0x21b 0x1>; > + bits = <4 6>; > + }; > + > + cpr_init_voltage0_pwrcl: ivolt0_pwrcl@21c { > + reg = <0x21c 0x1>; > + bits = <2 6>; > + }; > + > + /* CPR Target Quotients: Power Cluster */ > + cpr_quot3_pwrcl: quot3_pwrcl@21d { > + reg = <0x21d 0x2>; > + bits = <6 12>; > + }; > + > + cpr_quot2_pwrcl: quot2_pwrcl@21f { > + reg = <0x21f 0x2>; > + bits = <2 11>; > + }; > + > + cpr_quot1_pwrcl: quot1_pwrcl@220 { > + reg = <0x220 0x2>; > + bits = <6 12>; > + }; > + > + cpr_quot0_pwrcl: quot0_pwrcl@222 { > + reg = <0x222 0x2>; > + bits = <2 12>; > + }; > + > + /* CPR Quotient Offsets: Power Cluster */ > + cpr_quot_offset3_pwrcl: qoff3_pwrcl@226 { > + reg = <0x226 0x1>; > + bits = <1 7>; > + }; > + > + cpr_quot_offset2_pwrcl: qoff2_pwrcl@227 { > + reg = <0x227 0x1>; > + bits = <0 7>; > + }; > + > + cpr_quot_offset1_pwrcl: qoff1_pwrcl@227 { > + reg = <0x227 0x1>; > + bits = <7 6>; > + }; > + > + /* CPR Ring Oscillator: Performance Cluster */ > + cpr_ro_sel3_perfcl: rosel3_perfcl@229 { > + reg = <0x229 0x1>; > + bits = <6 4>; > + }; > + > + cpr_ro_sel2_perfcl: rosel2_perfcl@22a { > + reg = <0x22a 0x1>; > + bits = <2 4>; > + }; > + > + cpr_ro_sel1_perfcl: rosel1_perfcl@22a { > + reg = <0x22a 0x1>; > + bits = <6 4>; > + }; > + > + cpr_ro_sel0_perfcl: rosel0_perfcl@22b { > + reg = <0x22b 0x1>; > + bits = <2 4>; > + }; > + > + /* CPR Init Voltage: Performance Cluster */ > + cpr_init_voltage3_perfcl: ivolt3_perfcl@22b { > + reg = <0x22b 0x1>; > + bits = <6 6>; > + }; > + > + cpr_init_voltage2_perfcl: ivolt2_perfcl@22c { > + reg = <0x22c 0x1>; > + bits = <4 6>; > + }; > + > + cpr_init_voltage1_perfcl: ivolt1_perfcl@22d { > + reg = <0x22d 0x1>; > + bits = <2 6>; > + }; > + > + cpr_init_voltage0_perfcl: ivolt0_perfcl@22e { > + reg = <0x22e 0x1>; > + bits = <0 6>; > + }; > + > + /* CPR Target Quotients: Performance Cluster */ > + cpr_quot3_perfcl: quot3_perfcl@22f { > + reg = <0x22f 0x2>; > + bits = <4 11>; > + }; > + > + cpr_quot2_perfcl: quot2_perfcl@231 { > + reg = <0x231 0x2>; > + bits = <0 12>; > + }; > + > + cpr_quot1_perfcl: quot1_perfcl@232 { > + reg = <0x232 0x2>; > + bits = <4 12>; > + }; > + > + cpr_quot0_perfcl: quot0_perfcl@234 { > + reg = <0x234 0x2>; > + bits = <0 12>; > + }; > + > + /* CPR Quotient Offsets: Performance Cluster */ > + cpr_quot_offset3_perfcl: qoff3_perfcl@237 { > + reg = <0x237 0x1>; > + bits = <7 6>; > + }; > + > + cpr_quot_offset2_perfcl: qoff2_perfcl@238 { > + reg = <0x238 0x1>; > + bits = <6 7>; > + }; > + > + cpr_quot_offset1_perfcl: qoff1_perfcl@239 { > + reg = <0x239 0x1>; > + bits = <5 3>; > + }; > + > qusb2_hstx_trim: hstx-trim@23a { > reg = <0x23a 0x1>; > bits = <0 4>; > @@ -2998,6 +3790,87 @@ frame@17928000 { > }; > }; > > + apc_cprh: power-controller@179c8000 { > + compatible = "qcom,msm8998-cprh", "qcom,cprh"; > + reg = <0x179c8000 0x4000>, <0x179c4000 0x4000>; > + > + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; > + clock-names = "ref"; > + > + /* Set the CPR clock here, it needs to match XO */ > + assigned-clocks = <&gcc GCC_HMSS_RBCPR_CLK>; > + assigned-clock-rates = <19200000>; > + > + operating-points-v2 = <&cprh_opp_table>; > + power-domains = <&rpmpd MSM8998_VDDCX_AO>; > + #power-domain-cells = <1>; > + > + nvmem-cells = <&cpr_efuse_speedbin>, > + <&cpr_fuse_revision>, > + <&cpr_quot0_pwrcl>, > + <&cpr_quot1_pwrcl>, > + <&cpr_quot2_pwrcl>, > + <&cpr_quot3_pwrcl>, > + <&cpr_quot_offset1_pwrcl>, > + <&cpr_quot_offset2_pwrcl>, > + <&cpr_quot_offset3_pwrcl>, > + <&cpr_init_voltage0_pwrcl>, > + <&cpr_init_voltage1_pwrcl>, > + <&cpr_init_voltage2_pwrcl>, > + <&cpr_init_voltage3_pwrcl>, > + <&cpr_ro_sel0_pwrcl>, > + <&cpr_ro_sel1_pwrcl>, > + <&cpr_ro_sel2_pwrcl>, > + <&cpr_ro_sel3_pwrcl>, > + <&cpr_quot0_perfcl>, > + <&cpr_quot1_perfcl>, > + <&cpr_quot2_perfcl>, > + <&cpr_quot3_perfcl>, > + <&cpr_quot_offset1_perfcl>, > + <&cpr_quot_offset2_perfcl>, > + <&cpr_quot_offset3_perfcl>, > + <&cpr_init_voltage0_perfcl>, > + <&cpr_init_voltage1_perfcl>, > + <&cpr_init_voltage2_perfcl>, > + <&cpr_init_voltage3_perfcl>, > + <&cpr_ro_sel0_perfcl>, > + <&cpr_ro_sel1_perfcl>, > + <&cpr_ro_sel2_perfcl>, > + <&cpr_ro_sel3_perfcl>; > + nvmem-cell-names = "cpr_speed_bin", > + "cpr_fuse_revision", > + "cpr0_quotient1", > + "cpr0_quotient2", > + "cpr0_quotient3", > + "cpr0_quotient4", > + "cpr0_quotient_offset2", > + "cpr0_quotient_offset3", > + "cpr0_quotient_offset4", > + "cpr0_init_voltage1", > + "cpr0_init_voltage2", > + "cpr0_init_voltage3", > + "cpr0_init_voltage4", > + "cpr0_ring_osc1", > + "cpr0_ring_osc2", > + "cpr0_ring_osc3", > + "cpr0_ring_osc4", > + "cpr1_quotient1", > + "cpr1_quotient2", > + "cpr1_quotient3", > + "cpr1_quotient4", > + "cpr1_quotient_offset2", > + "cpr1_quotient_offset3", > + "cpr1_quotient_offset4", > + "cpr1_init_voltage1", > + "cpr1_init_voltage2", > + "cpr1_init_voltage3", > + "cpr1_init_voltage4", > + "cpr1_ring_osc1", > + "cpr1_ring_osc2", > + "cpr1_ring_osc3", > + "cpr1_ring_osc4"; > + }; > + > intc: interrupt-controller@17a00000 { > compatible = "arm,gic-v3"; > reg = <0x17a00000 0x10000>, /* GICD */ ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-01-16 17:26 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
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[not found] <20230116093845.72621-1-konrad.dybcio@linaro.org>
2023-01-16 9:38 ` [PATCH v9 2/6] dt-bindings: soc: qcom: cpr3: Add bindings for CPR3 driver Konrad Dybcio
2023-01-16 9:43 ` Konrad Dybcio
2023-01-16 11:26 ` Konrad Dybcio
2023-01-16 16:36 ` Rob Herring
2023-01-16 17:03 ` Konrad Dybcio
2023-01-16 9:38 ` [PATCH v9 3/6] dt-bindings: opp: v2-qcom-level: Let qcom,opp-fuse-level be a 2-long array Konrad Dybcio
2023-01-16 9:42 ` Viresh Kumar
2023-01-16 9:38 ` [PATCH v9 6/6] arm64: dts: qcom: msm8998: Configure CPRh Konrad Dybcio
2023-01-16 14:30 ` Konrad Dybcio
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