From: Abel Vesa <abel.vesa@linaro.org>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <andersson@kernel.org>,
Konrad Dybcio <konrad.dybcio@linaro.org>,
"vkoul@kernel.org" <vkoul@kernel.org>,
Kishon Vijay Abraham I <kishon@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Cc: linux-arm-msm@vger.kernel.org, linux-phy@lists.infradead.org,
devicetree@vger.kernel.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Johan Hovold <johan@kernel.org>
Subject: [PATCH v3 0/8] phy: qualcomm: Add PCIe support for SM8550
Date: Wed, 18 Jan 2023 02:53:20 +0200 [thread overview]
Message-ID: <20230118005328.2378792-1-abel.vesa@linaro.org> (raw)
This patchset relies on the following patchset:
https://lore.kernel.org/all/20230117224148.1914627-1-abel.vesa@linaro.org/
The v2 of this patchset is:
https://lore.kernel.org/all/20230118003834.2330028-1-abel.vesa@linaro.org/
Changes since v2:
* added back the binding compatible update patch
Abel Vesa (8):
dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550
phy: qcom-qmp: pcs: Add v6 register offsets
phy: qcom-qmp: pcs: Add v6.20 register offsets
phy: qcom-qmp: pcs-pcie: Add v6 register offsets
phy: qcom-qmp: pcs-pcie: Add v6.20 register offsets
phy: qcom-qmp: qserdes-txrx: Add v6.20 register offsets
phy: qcom-qmp: qserdes-lane-shared: Add v6 register offsets
phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs
.../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 2 +
drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 371 ++++++++++++++++++
.../phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h | 15 +
.../qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h | 23 ++
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h | 16 +
drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h | 18 +
.../phy-qcom-qmp-qserdes-ln-shrd-v6.h | 32 ++
.../phy-qcom-qmp-qserdes-txrx-v6_20.h | 45 +++
drivers/phy/qualcomm/phy-qcom-qmp.h | 6 +
9 files changed, 528 insertions(+)
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-pcie-v6_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-pcs-v6_20.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-ln-shrd-v6.h
create mode 100644 drivers/phy/qualcomm/phy-qcom-qmp-qserdes-txrx-v6_20.h
--
2.34.1
next reply other threads:[~2023-01-18 1:05 UTC|newest]
Thread overview: 21+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-01-18 0:53 Abel Vesa [this message]
2023-01-18 0:53 ` [PATCH v3 1/8] dt-bindings: phy: Add QMP PCIe PHY comptible for SM8550 Abel Vesa
2023-01-18 16:36 ` Rob Herring
2023-01-18 16:45 ` Johan Hovold
2023-01-18 21:25 ` Abel Vesa
2023-01-19 7:40 ` Johan Hovold
2023-01-18 0:53 ` [PATCH v3 2/8] phy: qcom-qmp: pcs: Add v6 register offsets Abel Vesa
2023-01-18 4:20 ` Dmitry Baryshkov
2023-01-18 0:53 ` [PATCH v3 3/8] phy: qcom-qmp: pcs: Add v6.20 " Abel Vesa
2023-01-18 4:25 ` Dmitry Baryshkov
2023-01-18 0:53 ` [PATCH v3 4/8] phy: qcom-qmp: pcs-pcie: Add v6 " Abel Vesa
2023-01-18 4:25 ` Dmitry Baryshkov
2023-01-18 0:53 ` [PATCH v3 5/8] phy: qcom-qmp: pcs-pcie: Add v6.20 " Abel Vesa
2023-01-18 4:26 ` Dmitry Baryshkov
2023-01-18 0:53 ` [PATCH v3 6/8] phy: qcom-qmp: qserdes-txrx: " Abel Vesa
2023-01-18 4:30 ` Dmitry Baryshkov
2023-01-18 0:53 ` [PATCH v3 7/8] phy: qcom-qmp: qserdes-lane-shared: Add v6 " Abel Vesa
2023-01-18 0:53 ` [PATCH v3 8/8] phy: qcom-qmp-pcie: Add support for SM8550 g3x2 and g4x2 PCIEs Abel Vesa
2023-01-18 4:34 ` Dmitry Baryshkov
2023-01-18 23:34 ` Abel Vesa
2023-01-19 13:07 ` Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230118005328.2378792-1-abel.vesa@linaro.org \
--to=abel.vesa@linaro.org \
--cc=agross@kernel.org \
--cc=andersson@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=johan@kernel.org \
--cc=kishon@kernel.org \
--cc=konrad.dybcio@linaro.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-phy@lists.infradead.org \
--cc=robh+dt@kernel.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).