From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CAC1C46467 for ; Wed, 18 Jan 2023 12:00:38 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229689AbjARMAh (ORCPT ); Wed, 18 Jan 2023 07:00:37 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230029AbjARMAH (ORCPT ); Wed, 18 Jan 2023 07:00:07 -0500 Received: from mail-wm1-x330.google.com (mail-wm1-x330.google.com [IPv6:2a00:1450:4864:20::330]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 07C6195755 for ; Wed, 18 Jan 2023 03:17:14 -0800 (PST) Received: by mail-wm1-x330.google.com with SMTP id c4-20020a1c3504000000b003d9e2f72093so1167846wma.1 for ; Wed, 18 Jan 2023 03:17:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Ax0S1Mi21dQMczSaAgM0TaYM+PtE4awHpXsqNp1yeTs=; b=LVO8wtaTw/mwetQHWmbQRBGMm1Qwm1fXYLm1TMwUAF0rVno1eQ4vfawC8DHGgibq85 Ca9IuilPgvfjwM7dPmJKpoLHPQ5t8tg1ITDXefjjYttak0nnHOVJG9bYNKic3uQ/NqaX rDj+UszO828Jvel8gZgKI2WU6kFW4aO3jcrlqQZC0VJXOQdRtpyGRr1ztBSyh8PQHE4C uTZftHL8faguXRqYtbMlMPdK4SIATcGt15ZsYErjJVPQpbyUtj9a72xHhQlotxaWS11n axniRJOKC1NJ3AElrqOKee4fpzy3vHCHRAb8wjQ09Q8ad1kg6+n9VfI0yXFnhEulGcNc bb/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ax0S1Mi21dQMczSaAgM0TaYM+PtE4awHpXsqNp1yeTs=; b=3a5q0DDuGeI5gm4gkT+Qb5Cecc9daO01APLlgcTXqF6bpF/7qDVpqa67EK54HvUILn bUWnb0IEL4+v884AftiyDlXWKDhti8GHUAImtljufLFuyYw3qh9n7nliRdd1Ra0oAy7I 5qfGM8jTMs8U2uBDlgdIBTThcGxngImiMNHAXTuVI8S6EFTJtNTzp9ehzAnV/JwkCb7I E/cyxOy11+ZNzR4zI8HV+OnRUbxIuSLEF8tXMc+PYYefq+4x3bYnuJRuRLEkOtlK6+rz W6cnZDbnLyHan8x42qv63nmUJ5KQoNTgRbwSy0PH6EebzHQWVgliODHeLNCMtiVDDOR3 /XPg== X-Gm-Message-State: AFqh2kpdLG5AadoaNE+TdaXVtUoAvY0bjmsBf9JZ7QbVt9Mx0EHzPkVb XjaW44YgS5FTJBUsqhi3LgDsNQ== X-Google-Smtp-Source: AMrXdXu/jsgeI9CfpoJSfBwQlQSHFQhbqZk8oQ0dhQ1qE3VJqvmj418GDaH2fhc0Fdp0lB7bGnPoRg== X-Received: by 2002:a05:600c:3c8a:b0:3da:2a78:d7a4 with SMTP id bg10-20020a05600c3c8a00b003da2a78d7a4mr6183108wmb.21.1674040633455; Wed, 18 Jan 2023 03:17:13 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id q10-20020a1cf30a000000b003d1e3b1624dsm1670998wmq.2.2023.01.18.03.17.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 18 Jan 2023 03:17:12 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Lorenzo Pieralisi , Rob Herring , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Krzysztof Kozlowski , Manivannan Sadhasivam Cc: linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List Subject: [PATCH v2 2/2] PCI: qcom: Add SM8550 PCIe support Date: Wed, 18 Jan 2023 13:17:04 +0200 Message-Id: <20230118111704.3553542-2-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230118111704.3553542-1-abel.vesa@linaro.org> References: <20230118111704.3553542-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add compatible for both PCIe found on SM8550. Also add the cnoc_pcie_sf_axi clock needed by the SM8550. Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio --- The v1 was here: https://lore.kernel.org/all/20221116123505.2760397-2-abel.vesa@linaro.org/ Changes since v1: * changed the subject line prefix for the patch to match the history, like Bjorn Helgaas suggested. * added Konrad's R-b tag drivers/pci/controller/dwc/pcie-qcom.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controller/dwc/pcie-qcom.c index 77e5dc7b88ad..85988b3fd4f6 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -182,7 +182,7 @@ struct qcom_pcie_resources_2_3_3 { /* 6 clocks typically, 7 for sm8250 */ struct qcom_pcie_resources_2_7_0 { - struct clk_bulk_data clks[12]; + struct clk_bulk_data clks[13]; int num_clks; struct regulator_bulk_data supplies[2]; struct reset_control *pci_reset; @@ -1208,6 +1208,7 @@ static int qcom_pcie_get_resources_2_7_0(struct qcom_pcie *pcie) res->clks[idx++].id = "noc_aggr_4"; res->clks[idx++].id = "noc_aggr_south_sf"; res->clks[idx++].id = "cnoc_qx"; + res->clks[idx++].id = "cnoc_pcie_sf_axi"; num_opt_clks = idx - num_clks; res->num_clks = idx; @@ -1828,6 +1829,7 @@ static const struct of_device_id qcom_pcie_match[] = { { .compatible = "qcom,pcie-sm8250", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie0", .data = &cfg_1_9_0 }, { .compatible = "qcom,pcie-sm8450-pcie1", .data = &cfg_1_9_0 }, + { .compatible = "qcom,pcie-sm8550", .data = &cfg_1_9_0 }, { } }; -- 2.34.1