From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B9650C54E94 for ; Thu, 26 Jan 2023 12:47:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S236188AbjAZMrT (ORCPT ); Thu, 26 Jan 2023 07:47:19 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:57124 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S236422AbjAZMrM (ORCPT ); Thu, 26 Jan 2023 07:47:12 -0500 Received: from mail-wr1-x436.google.com (mail-wr1-x436.google.com [IPv6:2a00:1450:4864:20::436]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 80D5A6D346 for ; Thu, 26 Jan 2023 04:47:05 -0800 (PST) Received: by mail-wr1-x436.google.com with SMTP id r2so1647591wrv.7 for ; Thu, 26 Jan 2023 04:47:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=7Hiqiqd1r7bxhHARO+brBurquXICZ+FcTy3sXinUo+w=; b=wWKOlLw8rfTnctLsMzyMyFdaHXAUqlNtWLv9hfwRYMCWd+cYvqxskBNosNjTs4S7Nf yE5k986ugAPQfFBSf0IKTekJL/+BTsP4170ikXfN0mA/vVhbwlqi2L/qfKgmWd629HEL 7v07altHpXx2oXep4eA4ZvgBnOeDWUA8tHqulJ0SfZIWdda64L0cSUm6ZYtNaqrcuDHe 38Epo150BZsuvGB+fpsc84ypijEu+4b6sRoQcLqhzLG6ecl8ofG5LdB8OAdGATLsNBNw HdQtoyFAsTHOXJGGG+oJPoeMuvLcbk8CB22OmbUZ4wgE7wEcyq/Wyu5o9s7L/IiPGAVW DK5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7Hiqiqd1r7bxhHARO+brBurquXICZ+FcTy3sXinUo+w=; b=HtLUcuMTtMBBoTGJihJCKxXqzMJw48lVlHJuFJSBBePNJwS4f9JzeQq0TNSntvUDsc eM4skuCilh3tnpSxSlXhi39WJc0wAkp4bizVlgFcurMUNyqNl7r4spIRUeL6McAJ/X3M VpWJAMDI/SyXs4V/VmAylUcUgirYsdRnOHtFxNLH6iu02hMwMY6VFVvDAx6wzOQGZJhO yCTDIREAdDSkPQOCX8kzsKdxVCZOI0hDeqLD+rSE3Exxg5a9A00wlU5LyT2jxeted0lF h4XKoLgFCbhyK4oZOJEQUi0hHWEwreDUCsXOTqynA4oLm5RkTKJxcD9jfHOlfL02LHIf OD1g== X-Gm-Message-State: AO0yUKVe37ZFVDWXij4ufOY3jfIw6cW88LB+obIG0ErVDywgklMtL+ZP ltlIkUJCmcz7F5CIDGVZbGhGqQ== X-Google-Smtp-Source: AK7set9q53x1okffv7MXEXBGbFJ2Lkvy3vzXs8pafMBOjEDFgac2KcQARMZDAHCW76jagk0jgidPYA== X-Received: by 2002:a5d:50c5:0:b0:2bf:b54c:6d19 with SMTP id f5-20020a5d50c5000000b002bfb54c6d19mr6804012wrt.10.1674737223931; Thu, 26 Jan 2023 04:47:03 -0800 (PST) Received: from hackbox.lan ([94.52.112.99]) by smtp.gmail.com with ESMTPSA id v11-20020adff68b000000b002bfb8f829eesm1198681wrp.71.2023.01.26.04.47.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 Jan 2023 04:47:03 -0800 (PST) From: Abel Vesa To: Andy Gross , Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , "vkoul@kernel.org" , Kishon Vijay Abraham I , Philipp Zabel Cc: linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, Linux Kernel Mailing List , linux-phy@lists.infradead.org Subject: [PATCH v2 5/8] phy: qcom-qmp: Add v6 DP register offsets Date: Thu, 26 Jan 2023 14:46:48 +0200 Message-Id: <20230126124651.1362533-6-abel.vesa@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20230126124651.1362533-1-abel.vesa@linaro.org> References: <20230126124651.1362533-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The new SM8550 SoC bumps up the HW version of QMP phy to v6. Add the new DP specific offsets in the generic qmp header file. Signed-off-by: Abel Vesa --- This patch did not exist in v1. Since then, the DP support has been added. drivers/phy/qualcomm/phy-qcom-qmp.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h index 148663ee713a..7ee4b0e07d11 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp.h +++ b/drivers/phy/qualcomm/phy-qcom-qmp.h @@ -134,4 +134,8 @@ #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 +/* Only for QMP V6 PHY - DP PHY registers */ +#define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS 0x0e0 +#define QSERDES_V6_DP_PHY_STATUS 0x0e4 + #endif -- 2.34.1