From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0F01CC636CC for ; Wed, 8 Feb 2023 06:57:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230078AbjBHG5V (ORCPT ); Wed, 8 Feb 2023 01:57:21 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36276 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229550AbjBHG5U (ORCPT ); Wed, 8 Feb 2023 01:57:20 -0500 Received: from mout.perfora.net (mout.perfora.net [74.208.4.196]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1DE16126D2; Tue, 7 Feb 2023 22:57:18 -0800 (PST) Received: from toolbox.int.toradex.com ([213.55.227.109]) by mrelay.perfora.net (mreueus002 [74.208.5.2]) with ESMTPSA (Nemesis) id 0MPF70-1pU4EJ11w8-004RfV; Wed, 08 Feb 2023 07:56:55 +0100 From: Marcel Ziswiler To: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org, Liu Ying , linux-imx@nxp.com, linux-arm-kernel@lists.infradead.org, Krzysztof Kozlowski , Philippe Schenker , Max Krummenacher , Marcel Ziswiler , Fabio Estevam , Krzysztof Kozlowski , Pengutronix Kernel Team , Rob Herring , Sascha Hauer , Shawn Guo Subject: [PATCH v7 01/10] arm64: dts: freescale: imx8-ss-lsio: add support for lsio_pwm0-3 Date: Wed, 8 Feb 2023 07:56:32 +0100 Message-Id: <20230208065641.23544-2-marcel@ziswiler.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230208065641.23544-1-marcel@ziswiler.com> References: <20230208065641.23544-1-marcel@ziswiler.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Provags-ID: V03:K1:N1bTkC3jSRgkS767lecp0Wnk01F9KE7l/IFW2rSOpoLc6Pquy8Z 0LYaKOM96b6ZXDkOIGRgeh61NFxQFL4hTJZJXZIbacdUtVZhvhEqifLltNm3mdf/0PEGTH5 2h8vTlxVtOSBGmiuE2XgDFSKTmUlBQZLjXqqeNhj6h7s5kvTfSdaMsR6hnqwadBjHDaUXjy XuiNze9fQSEKmBjM/x5bg== UI-OutboundReport: notjunk:1;M01:P0:jPRJjQIsEWY=;zFgaGDS8hVqK5Y+RSX4mY/lhEd5 vG11sYCZ/gvOp6I8G8ZM5eW8z6DyCdH0gmw6AIYTb32TJBAfqd8UyhG5nKwEpdqqLvmLt6jl/ xy22Rkr6IyiLUUqXaKv7dgiFuJ31pr6mJ5Ryfm++utqvZSfnQ9v8QKCsExyaAGTA1nIASIT+S CrBWHEDfrr76lbejRtmeFyQh+IpLckd2VvAiVp/2GV3HfzD4WRxM9VF3oP8eK6S2YnuuurO7S eKCye8Wv8ChCcT4QA4HxNH6U1EJ/C1ekGePhbexMWEcUVD0Tes+DzJofynyEr3wqS05nnNTcl qeWh2Q3QrF2EzLOa/PR/MwzZui3+a/+xhwYOU43AZkRGyzcLNmWXWp/5mqUVRjH9kzwsXPzyT H0LORIug3VsXF/tyf5bf+5CTYMUqi+7gchuTfwLGQb974xbT2O6kSHWcsb5yQYbu3Wv+snnbp M536mWRhrHk5hoIBXRMnRcZSnJV11g6AIXq1QOxpA372WJsSuRR3JL9UyyqA2KycU96bUdn6V eUKrOcjmaUMmTQ/G9/TTK6RHMrcxIPT/8YwXErNq9f6Vaj1sTshiuObZKe/btsHGWqt+k19hN +wTGq4oqeeQ2Z91R/Jl4ae3r9zX0sag6IWSQ1d/ZSv2fDyJk1U7c25gBBeZOQAtFrdwLvDcCi nNadLJnPCvZ3gHjsjOqOUrzHkDEkvv5zHUULjrAt4g== Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Philippe Schenker Add support for lsio_pwm0-3. Signed-off-by: Philippe Schenker Signed-off-by: Max Krummenacher Signed-off-by: Marcel Ziswiler --- (no changes since v1) .../boot/dts/freescale/imx8-ss-lsio.dtsi | 48 +++++++++++++++++++ 1 file changed, 48 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index 1f3d225e64ec..62b7f7a3e1bc 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -28,6 +28,54 @@ lsio_bus_clk: clock-lsio-bus { clock-output-names = "lsio_bus_clk"; }; + lsio_pwm0: pwm@5d000000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d000000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm0_lpcg 4>, + <&pwm0_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm1: pwm@5d010000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d010000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm1_lpcg 4>, + <&pwm1_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm2: pwm@5d020000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d020000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm2_lpcg 4>, + <&pwm2_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + + lsio_pwm3: pwm@5d030000 { + compatible = "fsl,imx27-pwm"; + reg = <0x5d030000 0x10000>; + clock-names = "ipg", "per"; + clocks = <&pwm3_lpcg 4>, + <&pwm3_lpcg 1>; + assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <2>; + status = "disabled"; + }; + lsio_gpio0: gpio@5d080000 { reg = <0x5d080000 0x10000>; interrupts = ; -- 2.36.1