* [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM
@ 2023-02-11 6:40 Sam Protsenko
2023-02-11 6:40 ` [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Sam Protsenko
` (9 more replies)
0 siblings, 10 replies; 14+ messages in thread
From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw)
To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki,
Rob Herring
Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa,
Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk,
devicetree, linux-arm-kernel, linux-kernel
As a part of preparation for PM enablement in Exynos850 clock driver,
this patch series implements CMU_G3D, and also main gate clocks for AUD
and HSI CMUs. The series brings corresponding changes to bindings, the
driver and SoC dts file.
Sam Protsenko (6):
dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D
dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks
clk: samsung: clk-pll: Implement pll0818x PLL type
clk: samsung: exynos850: Implement CMU_G3D domain
clk: samsung: exynos850: Add AUD and HSI main gate clocks
arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC
.../clock/samsung,exynos850-clock.yaml | 19 +++
arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 ++
drivers/clk/samsung/clk-exynos850.c | 139 ++++++++++++++++++
drivers/clk/samsung/clk-pll.c | 1 +
drivers/clk/samsung/clk-pll.h | 1 +
include/dt-bindings/clock/exynos850.h | 28 +++-
6 files changed, 194 insertions(+), 3 deletions(-)
--
2.39.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko 2023-02-14 23:56 ` Rob Herring 2023-02-11 6:40 ` [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Sam Protsenko ` (8 subsequent siblings) 9 siblings, 1 reply; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. Add clock indices and binding documentation for CMU_G3D. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- 2 files changed, 38 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml index 141cf173f87d..8aa87b8c1b33 100644 --- a/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml +++ b/Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml @@ -37,6 +37,7 @@ properties: - samsung,exynos850-cmu-cmgp - samsung,exynos850-cmu-core - samsung,exynos850-cmu-dpu + - samsung,exynos850-cmu-g3d - samsung,exynos850-cmu-hsi - samsung,exynos850-cmu-is - samsung,exynos850-cmu-mfcmscl @@ -169,6 +170,24 @@ allOf: - const: oscclk - const: dout_dpu + - if: + properties: + compatible: + contains: + const: samsung,exynos850-cmu-g3d + + then: + properties: + clocks: + items: + - description: External reference clock (26 MHz) + - description: G3D clock (from CMU_TOP) + + clock-names: + items: + - const: oscclk + - const: dout_g3d_switch + - if: properties: compatible: diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 88d5289883d3..8bb62e43fd60 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -85,7 +85,10 @@ #define CLK_DOUT_MFCMSCL_M2M 73 #define CLK_DOUT_MFCMSCL_MCSC 74 #define CLK_DOUT_MFCMSCL_JPEG 75 -#define TOP_NR_CLK 76 +#define CLK_MOUT_G3D_SWITCH 76 +#define CLK_GOUT_G3D_SWITCH 77 +#define CLK_DOUT_G3D_SWITCH 78 +#define TOP_NR_CLK 79 /* CMU_APM */ #define CLK_RCO_I3C_PMIC 1 @@ -195,6 +198,21 @@ #define CLK_GOUT_SYSREG_CMGP_PCLK 15 #define CMGP_NR_CLK 16 +/* CMU_G3D */ +#define CLK_FOUT_G3D_PLL 1 +#define CLK_MOUT_G3D_PLL 2 +#define CLK_MOUT_G3D_SWITCH_USER 3 +#define CLK_MOUT_G3D_BUSD 4 +#define CLK_DOUT_G3D_BUSP 5 +#define CLK_GOUT_G3D_CMU_G3D_PCLK 6 +#define CLK_GOUT_G3D_GPU_CLK 7 +#define CLK_GOUT_G3D_TZPC_PCLK 8 +#define CLK_GOUT_G3D_GRAY2BIN_CLK 9 +#define CLK_GOUT_G3D_BUSD_CLK 10 +#define CLK_GOUT_G3D_BUSP_CLK 11 +#define CLK_GOUT_G3D_SYSREG_PCLK 12 +#define G3D_NR_CLK 13 + /* CMU_HSI */ #define CLK_MOUT_HSI_BUS_USER 1 #define CLK_MOUT_HSI_MMC_CARD_USER 2 -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D 2023-02-11 6:40 ` [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Sam Protsenko @ 2023-02-14 23:56 ` Rob Herring 0 siblings, 0 replies; 14+ messages in thread From: Rob Herring @ 2023-02-14 23:56 UTC (permalink / raw) To: Sam Protsenko Cc: linux-arm-kernel, linux-clk, Krzysztof Kozlowski, Stephen Boyd, Chanwoo Choi, Alim Akhtar, David Virag, Chanho Park, linux-samsung-soc, devicetree, Tomasz Figa, Michael Turquette, Rob Herring, linux-kernel, Sumit Semwal, Sylwester Nawrocki On Sat, 11 Feb 2023 00:40:01 -0600, Sam Protsenko wrote: > CMU_G3D generates Gondul GPU and bus clocks for BLK_G3D. > Add clock indices and binding documentation for CMU_G3D. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > .../clock/samsung,exynos850-clock.yaml | 19 ++++++++++++++++++ > include/dt-bindings/clock/exynos850.h | 20 ++++++++++++++++++- > 2 files changed, 38 insertions(+), 1 deletion(-) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko 2023-02-11 6:40 ` [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko 2023-02-14 23:57 ` Rob Herring 2023-02-11 6:40 ` [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Sam Protsenko ` (7 subsequent siblings) 9 siblings, 1 reply; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- include/dt-bindings/clock/exynos850.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/include/dt-bindings/clock/exynos850.h b/include/dt-bindings/clock/exynos850.h index 8bb62e43fd60..afacba338c91 100644 --- a/include/dt-bindings/clock/exynos850.h +++ b/include/dt-bindings/clock/exynos850.h @@ -178,7 +178,8 @@ #define IOCLK_AUDIOCDCLK5 58 #define IOCLK_AUDIOCDCLK6 59 #define TICK_USB 60 -#define AUD_NR_CLK 61 +#define CLK_GOUT_AUD_CMU_AUD_PCLK 61 +#define AUD_NR_CLK 62 /* CMU_CMGP */ #define CLK_RCO_CMGP 1 @@ -227,7 +228,10 @@ #define CLK_GOUT_MMC_CARD_ACLK 11 #define CLK_GOUT_MMC_CARD_SDCLKIN 12 #define CLK_GOUT_SYSREG_HSI_PCLK 13 -#define HSI_NR_CLK 14 +#define CLK_GOUT_HSI_PPMU_ACLK 14 +#define CLK_GOUT_HSI_PPMU_PCLK 15 +#define CLK_GOUT_HSI_CMU_HSI_PCLK 16 +#define HSI_NR_CLK 17 /* CMU_IS */ #define CLK_MOUT_IS_BUS_USER 1 -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks 2023-02-11 6:40 ` [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Sam Protsenko @ 2023-02-14 23:57 ` Rob Herring 0 siblings, 0 replies; 14+ messages in thread From: Rob Herring @ 2023-02-14 23:57 UTC (permalink / raw) To: Sam Protsenko Cc: Sylwester Nawrocki, Stephen Boyd, linux-kernel, Sumit Semwal, Tomasz Figa, linux-clk, linux-arm-kernel, Michael Turquette, devicetree, David Virag, Krzysztof Kozlowski, Alim Akhtar, Chanwoo Choi, linux-samsung-soc, Rob Herring, Chanho Park On Sat, 11 Feb 2023 00:40:02 -0600, Sam Protsenko wrote: > Add main gate clocks for controlling AUD and HSI CMUs: > - gout_aud_cmu_aud_pclk > - gout_hsi_cmu_hsi_pclk > > While at it, add missing PPMU (Performance Profiling Monitor Unit) > clocks for CMU_HSI. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > include/dt-bindings/clock/exynos850.h | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > Acked-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko 2023-02-11 6:40 ` [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Sam Protsenko 2023-02-11 6:40 ` [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko 2023-02-11 6:40 ` [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain Sam Protsenko ` (6 subsequent siblings) 9 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, pll0818x is the same as pll0822x. The only difference is: - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) Add pll0818x type as an alias to pll0822x. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- drivers/clk/samsung/clk-pll.c | 1 + drivers/clk/samsung/clk-pll.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c index 5ceac4c25c1c..74934c6182ce 100644 --- a/drivers/clk/samsung/clk-pll.c +++ b/drivers/clk/samsung/clk-pll.c @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, init.ops = &samsung_pll35xx_clk_ops; break; case pll_1417x: + case pll_0818x: case pll_0822x: pll->enable_offs = PLL0822X_ENABLE_SHIFT; pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index 5d5a58d40e7e..0725d485c6ee 100644 --- a/drivers/clk/samsung/clk-pll.h +++ b/drivers/clk/samsung/clk-pll.h @@ -34,6 +34,7 @@ enum samsung_pll_type { pll_1451x, pll_1452x, pll_1460x, + pll_0818x, pll_0822x, pll_0831x, pll_142xx, -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko ` (2 preceding siblings ...) 2023-02-11 6:40 ` [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko 2023-02-11 6:40 ` [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Sam Protsenko ` (5 subsequent siblings) 9 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for BLK_G3D. This patch adds next clocks: - bus clocks in CMU_TOP for CMU_G3D - all internal CMU_G3D clocks - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and SysReg G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- drivers/clk/samsung/clk-exynos850.c | 121 ++++++++++++++++++++++++++++ 1 file changed, 121 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index 541761e96aeb..a24eff42baae 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -36,6 +36,7 @@ #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 @@ -57,6 +58,7 @@ #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c #define CLK_CON_DIV_CLKCMU_DPU 0x1840 +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 @@ -84,6 +86,7 @@ #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c @@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, CLK_CON_MUX_MUX_CLKCMU_DPU, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, @@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, CLK_CON_DIV_CLKCMU_CORE_SSS, CLK_CON_DIV_CLKCMU_DPU, + CLK_CON_DIV_CLKCMU_G3D_SWITCH, CLK_CON_DIV_CLKCMU_HSI_BUS, CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, CLK_CON_DIV_CLKCMU_HSI_USB20DRD, @@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst = { CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, CLK_CON_GAT_GATE_CLKCMU_DPU, + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, @@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", "dout_shared0_div2", "oscclk", "oscclk" }; PNAME(mout_core_sss_p) = { "dout_shared0_div3", "dout_shared1_div3", "dout_shared0_div4", "dout_shared1_div4" }; +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ +PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", + "dout_shared0_div3", "dout_shared1_div3" }; /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", "dout_shared1_div2" }; PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", @@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] __initconst = { MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), + /* G3D */ + MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), + /* HSI */ MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), @@ -357,6 +370,10 @@ static const struct samsung_div_clock top_div_clks[] __initconst = { DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", CLK_CON_DIV_CLKCMU_DPU, 0, 4), + /* G3D */ + DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), + /* HSI */ DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), @@ -417,6 +434,10 @@ static const struct samsung_gate_clock top_gate_clks[] __initconst = { GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), + /* G3D */ + GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), + /* HSI */ GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), @@ -992,6 +1013,103 @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = { .clk_name = "gout_clkcmu_cmgp_bus", }; +/* ---- CMU_G3D ------------------------------------------------------------- */ + +/* Register Offset definitions for CMU_G3D (0x11400000) */ +#define PLL_LOCKTIME_PLL_G3D 0x0000 +#define PLL_CON0_PLL_G3D 0x0100 +#define PLL_CON3_PLL_G3D 0x010c +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 +#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 +#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 +#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 +#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 +#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c +#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 +#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 +#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 +#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c + + +static const unsigned long g3d_clk_regs[] __initconst = { + PLL_LOCKTIME_PLL_G3D, + PLL_CON0_PLL_G3D, + PLL_CON3_PLL_G3D, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, + CLK_CON_DIV_DIV_CLK_G3D_BUSP, + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, + CLK_CON_GAT_CLK_G3D_GPU_CLK, + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, +}; + +/* List of parent clocks for Muxes in CMU_G3D */ +PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; +PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; +PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", "mout_g3d_switch_user" }; + +/* + * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not set + * for that PLL by default, so set_rate operation would fail. + */ +static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { + PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), +}; + +static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { + MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, + PLL_CON0_PLL_G3D, 4, 1), + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", + mout_g3d_switch_user_p, + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), + MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, + CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), +}; + +static const struct samsung_div_clock g3d_div_clks[] __initconst = { + DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", + CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), +}; + +static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { + GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", + "dout_g3d_busp", + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), + GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", + CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", + "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", "dout_g3d_busp", + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), +}; + +static const struct samsung_cmu_info g3d_cmu_info __initconst = { + .pll_clks = g3d_pll_clks, + .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), + .mux_clks = g3d_mux_clks, + .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), + .div_clks = g3d_div_clks, + .nr_div_clks = ARRAY_SIZE(g3d_div_clks), + .gate_clks = g3d_gate_clks, + .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), + .nr_clk_ids = G3D_NR_CLK, + .clk_regs = g3d_clk_regs, + .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), + .clk_name = "dout_g3d_switch", +}; + /* ---- CMU_HSI ------------------------------------------------------------- */ /* Register Offset definitions for CMU_HSI (0x13400000) */ @@ -1700,6 +1818,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = { }, { .compatible = "samsung,exynos850-cmu-cmgp", .data = &cmgp_cmu_info, + }, { + .compatible = "samsung,exynos850-cmu-g3d", + .data = &g3d_cmu_info, }, { .compatible = "samsung,exynos850-cmu-hsi", .data = &hsi_cmu_info, -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko ` (3 preceding siblings ...) 2023-02-11 6:40 ` [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko 2023-02-11 6:40 ` [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC Sam Protsenko ` (4 subsequent siblings) 9 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add main gate clocks for controlling AUD and HSI CMUs: - gout_aud_cmu_aud_pclk - gout_hsi_cmu_hsi_pclk Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot otherwise. While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks for CMU_HSI. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+) diff --git a/drivers/clk/samsung/clk-exynos850.c b/drivers/clk/samsung/clk-exynos850.c index a24eff42baae..3d776d57cc8f 100644 --- a/drivers/clk/samsung/clk-exynos850.c +++ b/drivers/clk/samsung/clk-exynos850.c @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info __initconst = { #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst = { CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] __initconst = { }; static const struct samsung_gate_clock aud_gate_clks[] __initconst = { + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", + "dout_aud_busd", + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", "mout_aud_cpu_hch", CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct samsung_cmu_info g3d_cmu_info __initconst = { #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] __initconst = { PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, CLK_CON_MUX_MUX_CLK_HSI_RTC, + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] __initconst = { }; static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", + "mout_hsi_bus_user", + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", "mout_hsi_mmc_card_user", CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, 0), + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", "mout_hsi_bus_user", + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", "mout_hsi_bus_user", CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC 2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko ` (4 preceding siblings ...) 2023-02-11 6:40 ` [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Sam Protsenko @ 2023-02-11 6:40 ` Sam Protsenko [not found] ` <CGME20230211063955epcas2p177f52416ffb66cffa368fde02ee40411@epcms2p3> ` (3 subsequent siblings) 9 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2023-02-11 6:40 UTC (permalink / raw) To: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, Chanho Park, Alim Akhtar, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc, linux-clk, devicetree, linux-arm-kernel, linux-kernel Add missing G3D clock domain to Exynos850 SoC device tree. Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> --- arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi b/arch/arm64/boot/dts/exynos/exynos850.dtsi index a38fe5129937..d67e98120313 100644 --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi @@ -245,6 +245,15 @@ cmu_peri: clock-controller@10030000 { "dout_peri_uart", "dout_peri_ip"; }; + cmu_g3d: clock-controller@11400000 { + compatible = "samsung,exynos850-cmu-g3d"; + reg = <0x11400000 0x8000>; + #clock-cells = <1>; + + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; + clock-names = "oscclk", "dout_g3d_switch"; + }; + cmu_apm: clock-controller@11800000 { compatible = "samsung,exynos850-cmu-apm"; reg = <0x11800000 0x8000>; -- 2.39.1 ^ permalink raw reply related [flat|nested] 14+ messages in thread
[parent not found: <CGME20230211063955epcas2p177f52416ffb66cffa368fde02ee40411@epcms2p3>]
* RE: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type [not found] ` <CGME20230211063955epcas2p177f52416ffb66cffa368fde02ee40411@epcms2p3> @ 2023-02-15 2:38 ` CHANHO PARK 0 siblings, 0 replies; 14+ messages in thread From: CHANHO PARK @ 2023-02-15 2:38 UTC (permalink / raw) To: Sam Protsenko, Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, ALIM AKHTAR, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org > Subject: [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type > > pll0818x PLL is used in Exynos850 SoC for CMU_G3D PLL. Operation-wise, > pll0818x is the same as pll0822x. The only difference is: > - pl0822x is integer PLL with Middle FVCO (950 to 2400 MHz) > - pl0818x is integer PLL with Low FVCO (600 to 1200 MHz) > > Add pll0818x type as an alias to pll0822x. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> > --- > drivers/clk/samsung/clk-pll.c | 1 + > drivers/clk/samsung/clk-pll.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 5ceac4c25c1c..74934c6182ce 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -1314,6 +1314,7 @@ static void __init _samsung_clk_register_pll(struct > samsung_clk_provider *ctx, > init.ops = &samsung_pll35xx_clk_ops; > break; > case pll_1417x: > + case pll_0818x: > case pll_0822x: > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; diff --git > a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h index > 5d5a58d40e7e..0725d485c6ee 100644 > --- a/drivers/clk/samsung/clk-pll.h > +++ b/drivers/clk/samsung/clk-pll.h > @@ -34,6 +34,7 @@ enum samsung_pll_type { > pll_1451x, > pll_1452x, > pll_1460x, > + pll_0818x, > pll_0822x, > pll_0831x, > pll_142xx, > -- > 2.39.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <CGME20230211063956epcas2p423cb99655dcfdb34c6847bb228aa7324@epcms2p2>]
* RE: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks [not found] ` <CGME20230211063956epcas2p423cb99655dcfdb34c6847bb228aa7324@epcms2p2> @ 2023-02-15 2:40 ` CHANHO PARK 2023-02-23 2:27 ` Sam Protsenko 0 siblings, 1 reply; 14+ messages in thread From: CHANHO PARK @ 2023-02-15 2:40 UTC (permalink / raw) To: Sam Protsenko, Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, ALIM AKHTAR, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org > -----Original Message----- > From: Sam Protsenko <semen.protsenko@linaro.org> > Sent: Saturday, February 11, 2023 3:40 PM > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > Herring <robh+dt@kernel.org> > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate > clocks > > Add main gate clocks for controlling AUD and HSI CMUs: > - gout_aud_cmu_aud_pclk > - gout_hsi_cmu_hsi_pclk > > Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot > otherwise. > > While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks > for CMU_HSI. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos850.c > b/drivers/clk/samsung/clk-exynos850.c > index a24eff42baae..3d776d57cc8f 100644 > --- a/drivers/clk/samsung/clk-exynos850.c > +++ b/drivers/clk/samsung/clk-exynos850.c > @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info > __initconst = { > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c > +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 > #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c > #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 > @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst > = { > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, > CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, > @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] > __initconst = { }; > > static const struct samsung_gate_clock aud_gate_clks[] __initconst = { > + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", > + "dout_aud_busd", > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), > GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", > "mout_aud_cpu_hch", > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), > GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", > "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct > samsung_cmu_info g3d_cmu_info __initconst = { > #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 > #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 > #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 > +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 > #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 > +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c > +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 > #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 > @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] > __initconst = { > PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, > PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, > CLK_CON_MUX_MUX_CLK_HSI_RTC, > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, > CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, > CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, > CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, > @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] > __initconst = { }; > > static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { > + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", > + "mout_hsi_bus_user", > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), You'll need to put /* TODO: */ tag or use CLK_IS_CRITICAL if you make sure it is the critical clock. > GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), > GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", > @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock > hsi_gate_clks[] __initconst = { > GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", > "mout_hsi_mmc_card_user", > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, > 0), > + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", > "mout_hsi_bus_user", > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), > + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", > "mout_hsi_bus_user", > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), > GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", > "mout_hsi_bus_user", > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), > -- > 2.39.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks 2023-02-15 2:40 ` [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks CHANHO PARK @ 2023-02-23 2:27 ` Sam Protsenko 0 siblings, 0 replies; 14+ messages in thread From: Sam Protsenko @ 2023-02-23 2:27 UTC (permalink / raw) To: chanho61.park Cc: Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring, David Virag, ALIM AKHTAR, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org On Tue, 14 Feb 2023 at 20:41, CHANHO PARK <chanho61.park@samsung.com> wrote: > > > -----Original Message----- > > From: Sam Protsenko <semen.protsenko@linaro.org> > > Sent: Saturday, February 11, 2023 3:40 PM > > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > > Herring <robh+dt@kernel.org> > > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > > Subject: [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate > > clocks > > > > Add main gate clocks for controlling AUD and HSI CMUs: > > - gout_aud_cmu_aud_pclk > > - gout_hsi_cmu_hsi_pclk > > > > Those clocks were marked as CLK_IGNORE_UNUSED, as system hangs on boot > > otherwise. > > > > While at it, add missing PPMU (Performance Profiling Monitor Unit) clocks > > for CMU_HSI. > > > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > > --- > > drivers/clk/samsung/clk-exynos850.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/clk/samsung/clk-exynos850.c > > b/drivers/clk/samsung/clk-exynos850.c > > index a24eff42baae..3d776d57cc8f 100644 > > --- a/drivers/clk/samsung/clk-exynos850.c > > +++ b/drivers/clk/samsung/clk-exynos850.c > > @@ -674,6 +674,7 @@ static const struct samsung_cmu_info apm_cmu_info > > __initconst = { > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4 0x2014 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5 0x2018 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6 0x201c > > +#define CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK 0x2020 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_ACLK 0x2048 > > #define CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY 0x204c > > #define CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB 0x2050 > > @@ -729,6 +730,7 @@ static const unsigned long aud_clk_regs[] __initconst > > = { > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF4, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF5, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_UAIF6, > > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, > > CLK_CON_GAT_GOUT_AUD_ABOX_ACLK, > > CLK_CON_GAT_GOUT_AUD_ABOX_BCLK_SPDY, > > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_ASB, > > @@ -848,6 +850,9 @@ static const struct samsung_div_clock aud_div_clks[] > > __initconst = { }; > > > > static const struct samsung_gate_clock aud_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_AUD_CMU_AUD_PCLK, "gout_aud_cmu_aud_pclk", > > + "dout_aud_busd", > > + CLK_CON_GAT_CLK_AUD_CMU_AUD_PCLK, 21, CLK_IGNORE_UNUSED, 0), > > GATE(CLK_GOUT_AUD_CA32_CCLK, "gout_aud_ca32_cclk", > > "mout_aud_cpu_hch", > > CLK_CON_GAT_GOUT_AUD_ABOX_CCLK_CA32, 21, 0, 0), > > GATE(CLK_GOUT_AUD_ASB_CCLK, "gout_aud_asb_cclk", > > "dout_aud_cpu_aclk", @@ -1117,12 +1122,15 @@ static const struct > > samsung_cmu_info g3d_cmu_info __initconst = { > > #define PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER 0x0610 > > #define PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER 0x0620 > > #define CLK_CON_MUX_MUX_CLK_HSI_RTC 0x1000 > > +#define CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK 0x2000 > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV 0x2008 > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50 0x200c > > #define CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26 0x2010 > > #define CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK 0x2018 > > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK 0x2024 > > #define CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN 0x2028 > > +#define CLK_CON_GAT_GOUT_HSI_PPMU_ACLK 0x202c > > +#define CLK_CON_GAT_GOUT_HSI_PPMU_PCLK 0x2030 > > #define CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK 0x2038 > > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20 0x203c > > #define CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY 0x2040 > > @@ -1132,12 +1140,15 @@ static const unsigned long hsi_clk_regs[] > > __initconst = { > > PLL_CON0_MUX_CLKCMU_HSI_MMC_CARD_USER, > > PLL_CON0_MUX_CLKCMU_HSI_USB20DRD_USER, > > CLK_CON_MUX_MUX_CLK_HSI_RTC, > > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_REF_CLK_50, > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_PHY_REFCLK_26, > > CLK_CON_GAT_GOUT_HSI_GPIO_HSI_PCLK, > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_I_ACLK, > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, > > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, > > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, > > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, > > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_ACLK_PHYCTRL_20, > > CLK_CON_GAT_GOUT_HSI_USB20DRD_TOP_BUS_CLK_EARLY, > > @@ -1163,6 +1174,9 @@ static const struct samsung_mux_clock hsi_mux_clks[] > > __initconst = { }; > > > > static const struct samsung_gate_clock hsi_gate_clks[] __initconst = { > > + GATE(CLK_GOUT_HSI_CMU_HSI_PCLK, "gout_hsi_cmu_hsi_pclk", > > + "mout_hsi_bus_user", > > + CLK_CON_GAT_CLK_HSI_CMU_HSI_PCLK, 21, CLK_IGNORE_UNUSED, 0), > > You'll need to put /* TODO: */ tag or use CLK_IS_CRITICAL if you make sure it is the critical clock. > Thanks for the review! I'll add the comment for now, as it's done in other CMUs for similar clocks. As for making it critical: maybe I'll do it as a part of PM enablement, which I'm working on right now (if it's needed). But in that case I'd like to provide a separate patch for making all similar clocks (XXX_CMU_XXX) critical, so not in this patch. Will send v2 soon. > > GATE(CLK_GOUT_USB_RTC_CLK, "gout_usb_rtc", "mout_hsi_rtc", > > CLK_CON_GAT_HSI_USB20DRD_TOP_I_RTC_CLK__ALV, 21, 0, 0), > > GATE(CLK_GOUT_USB_REF_CLK, "gout_usb_ref", "mout_hsi_usb20drd_user", > > @@ -1177,6 +1191,10 @@ static const struct samsung_gate_clock > > hsi_gate_clks[] __initconst = { > > GATE(CLK_GOUT_MMC_CARD_SDCLKIN, "gout_mmc_card_sdclkin", > > "mout_hsi_mmc_card_user", > > CLK_CON_GAT_GOUT_HSI_MMC_CARD_SDCLKIN, 21, CLK_SET_RATE_PARENT, > > 0), > > + GATE(CLK_GOUT_HSI_PPMU_ACLK, "gout_hsi_ppmu_aclk", > > "mout_hsi_bus_user", > > + CLK_CON_GAT_GOUT_HSI_PPMU_ACLK, 21, 0, 0), > > + GATE(CLK_GOUT_HSI_PPMU_PCLK, "gout_hsi_ppmu_pclk", > > "mout_hsi_bus_user", > > + CLK_CON_GAT_GOUT_HSI_PPMU_PCLK, 21, 0, 0), > > GATE(CLK_GOUT_SYSREG_HSI_PCLK, "gout_sysreg_hsi_pclk", > > "mout_hsi_bus_user", > > CLK_CON_GAT_GOUT_HSI_SYSREG_HSI_PCLK, 21, 0, 0), > > -- > > 2.39.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <CGME20230211063957epcas2p2302d93ee2aeb2c5e680b771aa8bbc785@epcms2p4>]
* RE: [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain [not found] ` <CGME20230211063957epcas2p2302d93ee2aeb2c5e680b771aa8bbc785@epcms2p4> @ 2023-02-15 3:24 ` CHANHO PARK 0 siblings, 0 replies; 14+ messages in thread From: CHANHO PARK @ 2023-02-15 3:24 UTC (permalink / raw) To: Sam Protsenko, Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, ALIM AKHTAR, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org > -----Original Message----- > From: Sam Protsenko <semen.protsenko@linaro.org> > Sent: Saturday, February 11, 2023 3:40 PM > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > Herring <robh+dt@kernel.org> > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain > > CMU_G3D clock domain provides clocks for Mali-G52 GPU and bus clocks for > BLK_G3D. > > This patch adds next clocks: > - bus clocks in CMU_TOP for CMU_G3D > - all internal CMU_G3D clocks > - leaf clocks for GPU, TZPC (TrustZone Protection Controller) and > SysReg > > G3D_CMU_G3D clock was marked as CLK_IGNORE_UNUSED, as system hangs on boot > otherwise. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> > --- > drivers/clk/samsung/clk-exynos850.c | 121 ++++++++++++++++++++++++++++ > 1 file changed, 121 insertions(+) > > diff --git a/drivers/clk/samsung/clk-exynos850.c > b/drivers/clk/samsung/clk-exynos850.c > index 541761e96aeb..a24eff42baae 100644 > --- a/drivers/clk/samsung/clk-exynos850.c > +++ b/drivers/clk/samsung/clk-exynos850.c > @@ -36,6 +36,7 @@ > #define CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD 0x101c > #define CLK_CON_MUX_MUX_CLKCMU_CORE_SSS 0x1020 > #define CLK_CON_MUX_MUX_CLKCMU_DPU 0x1034 > +#define CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH 0x1038 > #define CLK_CON_MUX_MUX_CLKCMU_HSI_BUS 0x103c > #define CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD 0x1040 > #define CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD 0x1044 > @@ -57,6 +58,7 @@ > #define CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD 0x1828 > #define CLK_CON_DIV_CLKCMU_CORE_SSS 0x182c > #define CLK_CON_DIV_CLKCMU_DPU 0x1840 > +#define CLK_CON_DIV_CLKCMU_G3D_SWITCH 0x1844 > #define CLK_CON_DIV_CLKCMU_HSI_BUS 0x1848 > #define CLK_CON_DIV_CLKCMU_HSI_MMC_CARD 0x184c > #define CLK_CON_DIV_CLKCMU_HSI_USB20DRD 0x1850 > @@ -84,6 +86,7 @@ > #define CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD 0x2024 > #define CLK_CON_GAT_GATE_CLKCMU_CORE_SSS 0x2028 > #define CLK_CON_GAT_GATE_CLKCMU_DPU 0x203c > +#define CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH 0x2040 > #define CLK_CON_GAT_GATE_CLKCMU_HSI_BUS 0x2044 > #define CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD 0x2048 > #define CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD 0x204c > @@ -116,6 +119,7 @@ static const unsigned long top_clk_regs[] __initconst > = { > CLK_CON_MUX_MUX_CLKCMU_CORE_MMC_EMBD, > CLK_CON_MUX_MUX_CLKCMU_CORE_SSS, > CLK_CON_MUX_MUX_CLKCMU_DPU, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, > CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, > CLK_CON_MUX_MUX_CLKCMU_HSI_MMC_CARD, > CLK_CON_MUX_MUX_CLKCMU_HSI_USB20DRD, > @@ -137,6 +141,7 @@ static const unsigned long top_clk_regs[] __initconst > = { > CLK_CON_DIV_CLKCMU_CORE_MMC_EMBD, > CLK_CON_DIV_CLKCMU_CORE_SSS, > CLK_CON_DIV_CLKCMU_DPU, > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, > CLK_CON_DIV_CLKCMU_HSI_BUS, > CLK_CON_DIV_CLKCMU_HSI_MMC_CARD, > CLK_CON_DIV_CLKCMU_HSI_USB20DRD, > @@ -164,6 +169,7 @@ static const unsigned long top_clk_regs[] __initconst > = { > CLK_CON_GAT_GATE_CLKCMU_CORE_MMC_EMBD, > CLK_CON_GAT_GATE_CLKCMU_CORE_SSS, > CLK_CON_GAT_GATE_CLKCMU_DPU, > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, > CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, > CLK_CON_GAT_GATE_CLKCMU_HSI_MMC_CARD, > CLK_CON_GAT_GATE_CLKCMU_HSI_USB20DRD, > @@ -216,6 +222,9 @@ PNAME(mout_core_mmc_embd_p) = { "oscclk", > "dout_shared0_div2", > "oscclk", "oscclk" }; > PNAME(mout_core_sss_p) = { "dout_shared0_div3", > "dout_shared1_div3", > "dout_shared0_div4", "dout_shared1_div4" }; > +/* List of parent clocks for Muxes in CMU_TOP: for CMU_G3D */ > +PNAME(mout_g3d_switch_p) = { "dout_shared0_div2", "dout_shared1_div2", > + "dout_shared0_div3", "dout_shared1_div3" }; > /* List of parent clocks for Muxes in CMU_TOP: for CMU_HSI */ > PNAME(mout_hsi_bus_p) = { "dout_shared0_div2", > "dout_shared1_div2" }; > PNAME(mout_hsi_mmc_card_p) = { "oscclk", "dout_shared0_div2", > @@ -283,6 +292,10 @@ static const struct samsung_mux_clock top_mux_clks[] > __initconst = { > MUX(CLK_MOUT_DPU, "mout_dpu", mout_dpu_p, > CLK_CON_MUX_MUX_CLKCMU_DPU, 0, 2), > > + /* G3D */ > + MUX(CLK_MOUT_G3D_SWITCH, "mout_g3d_switch", mout_g3d_switch_p, > + CLK_CON_MUX_MUX_CLKCMU_G3D_SWITCH, 0, 2), > + > /* HSI */ > MUX(CLK_MOUT_HSI_BUS, "mout_hsi_bus", mout_hsi_bus_p, > CLK_CON_MUX_MUX_CLKCMU_HSI_BUS, 0, 1), @@ -357,6 +370,10 @@ > static const struct samsung_div_clock top_div_clks[] __initconst = { > DIV(CLK_DOUT_DPU, "dout_dpu", "gout_dpu", > CLK_CON_DIV_CLKCMU_DPU, 0, 4), > > + /* G3D */ > + DIV(CLK_DOUT_G3D_SWITCH, "dout_g3d_switch", "gout_g3d_switch", > + CLK_CON_DIV_CLKCMU_G3D_SWITCH, 0, 3), > + > /* HSI */ > DIV(CLK_DOUT_HSI_BUS, "dout_hsi_bus", "gout_hsi_bus", > CLK_CON_DIV_CLKCMU_HSI_BUS, 0, 4), @@ -417,6 +434,10 @@ static > const struct samsung_gate_clock top_gate_clks[] __initconst = { > GATE(CLK_GOUT_DPU, "gout_dpu", "mout_dpu", > CLK_CON_GAT_GATE_CLKCMU_DPU, 21, 0, 0), > > + /* G3D */ > + GATE(CLK_GOUT_G3D_SWITCH, "gout_g3d_switch", "mout_g3d_switch", > + CLK_CON_GAT_GATE_CLKCMU_G3D_SWITCH, 21, 0, 0), > + > /* HSI */ > GATE(CLK_GOUT_HSI_BUS, "gout_hsi_bus", "mout_hsi_bus", > CLK_CON_GAT_GATE_CLKCMU_HSI_BUS, 21, 0, 0), @@ -992,6 +1013,103 > @@ static const struct samsung_cmu_info cmgp_cmu_info __initconst = { > .clk_name = "gout_clkcmu_cmgp_bus", > }; > > +/* ---- CMU_G3D > +------------------------------------------------------------- */ > + > +/* Register Offset definitions for CMU_G3D (0x11400000) */ > +#define PLL_LOCKTIME_PLL_G3D 0x0000 > +#define PLL_CON0_PLL_G3D 0x0100 > +#define PLL_CON3_PLL_G3D 0x010c > +#define PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER 0x0600 > +#define CLK_CON_MUX_MUX_CLK_G3D_BUSD 0x1000 > +#define CLK_CON_DIV_DIV_CLK_G3D_BUSP 0x1804 > +#define CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK 0x2000 > +#define CLK_CON_GAT_CLK_G3D_GPU_CLK 0x2004 > +#define CLK_CON_GAT_GOUT_G3D_TZPC_PCLK 0x200c > +#define CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK 0x2010 > +#define CLK_CON_GAT_GOUT_G3D_BUSD_CLK 0x2024 > +#define CLK_CON_GAT_GOUT_G3D_BUSP_CLK 0x2028 > +#define CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK 0x202c > + > + Nit: double empty lines. Otherwise, looks good to me :) Reviewed-by: Chanho Park <chanho61.park@samsung.com> > +static const unsigned long g3d_clk_regs[] __initconst = { > + PLL_LOCKTIME_PLL_G3D, > + PLL_CON0_PLL_G3D, > + PLL_CON3_PLL_G3D, > + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, > + CLK_CON_MUX_MUX_CLK_G3D_BUSD, > + CLK_CON_DIV_DIV_CLK_G3D_BUSP, > + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, > + CLK_CON_GAT_CLK_G3D_GPU_CLK, > + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, > + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, > + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, > + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, > + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, > +}; > + > +/* List of parent clocks for Muxes in CMU_G3D */ > +PNAME(mout_g3d_pll_p) = { "oscclk", "fout_g3d_pll" }; > +PNAME(mout_g3d_switch_user_p) = { "oscclk", "dout_g3d_switch" }; > +PNAME(mout_g3d_busd_p) = { "mout_g3d_pll", > "mout_g3d_switch_user" }; > + > +/* > + * Do not provide PLL table to PLL_G3D, as MANUAL_PLL_CTRL bit is not > +set > + * for that PLL by default, so set_rate operation would fail. > + */ > +static const struct samsung_pll_clock g3d_pll_clks[] __initconst = { > + PLL(pll_0818x, CLK_FOUT_G3D_PLL, "fout_g3d_pll", "oscclk", > + PLL_LOCKTIME_PLL_G3D, PLL_CON3_PLL_G3D, NULL), }; > + > +static const struct samsung_mux_clock g3d_mux_clks[] __initconst = { > + MUX(CLK_MOUT_G3D_PLL, "mout_g3d_pll", mout_g3d_pll_p, > + PLL_CON0_PLL_G3D, 4, 1), > + MUX(CLK_MOUT_G3D_SWITCH_USER, "mout_g3d_switch_user", > + mout_g3d_switch_user_p, > + PLL_CON0_MUX_CLKCMU_G3D_SWITCH_USER, 4, 1), > + MUX(CLK_MOUT_G3D_BUSD, "mout_g3d_busd", mout_g3d_busd_p, > + CLK_CON_MUX_MUX_CLK_G3D_BUSD, 0, 1), }; > + > +static const struct samsung_div_clock g3d_div_clks[] __initconst = { > + DIV(CLK_DOUT_G3D_BUSP, "dout_g3d_busp", "mout_g3d_busd", > + CLK_CON_DIV_DIV_CLK_G3D_BUSP, 0, 3), }; > + > +static const struct samsung_gate_clock g3d_gate_clks[] __initconst = { > + GATE(CLK_GOUT_G3D_CMU_G3D_PCLK, "gout_g3d_cmu_g3d_pclk", > + "dout_g3d_busp", > + CLK_CON_GAT_CLK_G3D_CMU_G3D_PCLK, 21, CLK_IGNORE_UNUSED, 0), > + GATE(CLK_GOUT_G3D_GPU_CLK, "gout_g3d_gpu_clk", "mout_g3d_busd", > + CLK_CON_GAT_CLK_G3D_GPU_CLK, 21, 0, 0), > + GATE(CLK_GOUT_G3D_TZPC_PCLK, "gout_g3d_tzpc_pclk", "dout_g3d_busp", > + CLK_CON_GAT_GOUT_G3D_TZPC_PCLK, 21, 0, 0), > + GATE(CLK_GOUT_G3D_GRAY2BIN_CLK, "gout_g3d_gray2bin_clk", > + "mout_g3d_busd", > + CLK_CON_GAT_GOUT_G3D_GRAY2BIN_CLK, 21, 0, 0), > + GATE(CLK_GOUT_G3D_BUSD_CLK, "gout_g3d_busd_clk", "mout_g3d_busd", > + CLK_CON_GAT_GOUT_G3D_BUSD_CLK, 21, 0, 0), > + GATE(CLK_GOUT_G3D_BUSP_CLK, "gout_g3d_busp_clk", "dout_g3d_busp", > + CLK_CON_GAT_GOUT_G3D_BUSP_CLK, 21, 0, 0), > + GATE(CLK_GOUT_G3D_SYSREG_PCLK, "gout_g3d_sysreg_pclk", > "dout_g3d_busp", > + CLK_CON_GAT_GOUT_G3D_SYSREG_PCLK, 21, 0, 0), }; > + > +static const struct samsung_cmu_info g3d_cmu_info __initconst = { > + .pll_clks = g3d_pll_clks, > + .nr_pll_clks = ARRAY_SIZE(g3d_pll_clks), > + .mux_clks = g3d_mux_clks, > + .nr_mux_clks = ARRAY_SIZE(g3d_mux_clks), > + .div_clks = g3d_div_clks, > + .nr_div_clks = ARRAY_SIZE(g3d_div_clks), > + .gate_clks = g3d_gate_clks, > + .nr_gate_clks = ARRAY_SIZE(g3d_gate_clks), > + .nr_clk_ids = G3D_NR_CLK, > + .clk_regs = g3d_clk_regs, > + .nr_clk_regs = ARRAY_SIZE(g3d_clk_regs), > + .clk_name = "dout_g3d_switch", > +}; > + > /* ---- CMU_HSI --------------------------------------------------------- > ---- */ > > /* Register Offset definitions for CMU_HSI (0x13400000) */ @@ -1700,6 > +1818,9 @@ static const struct of_device_id exynos850_cmu_of_match[] = { > }, { > .compatible = "samsung,exynos850-cmu-cmgp", > .data = &cmgp_cmu_info, > + }, { > + .compatible = "samsung,exynos850-cmu-g3d", > + .data = &g3d_cmu_info, > }, { > .compatible = "samsung,exynos850-cmu-hsi", > .data = &hsi_cmu_info, > -- > 2.39.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
[parent not found: <CGME20230211063959epcas2p2500790b0402f151030ac65d405419649@epcms2p5>]
* RE: [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC [not found] ` <CGME20230211063959epcas2p2500790b0402f151030ac65d405419649@epcms2p5> @ 2023-02-15 3:52 ` CHANHO PARK 0 siblings, 0 replies; 14+ messages in thread From: CHANHO PARK @ 2023-02-15 3:52 UTC (permalink / raw) To: Sam Protsenko, Krzysztof Kozlowski, Chanwoo Choi, Sylwester Nawrocki, Rob Herring Cc: David Virag, ALIM AKHTAR, Sumit Semwal, Tomasz Figa, Michael Turquette, Stephen Boyd, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org > -----Original Message----- > From: Sam Protsenko <semen.protsenko@linaro.org> > Sent: Saturday, February 11, 2023 3:40 PM > To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>; Chanwoo Choi > <cw00.choi@samsung.com>; Sylwester Nawrocki <s.nawrocki@samsung.com>; Rob > Herring <robh+dt@kernel.org> > Cc: David Virag <virag.david003@gmail.com>; Chanho Park > <chanho61.park@samsung.com>; Alim Akhtar <alim.akhtar@samsung.com>; Sumit > Semwal <sumit.semwal@linaro.org>; Tomasz Figa <tomasz.figa@gmail.com>; > Michael Turquette <mturquette@baylibre.com>; Stephen Boyd > <sboyd@kernel.org>; linux-samsung-soc@vger.kernel.org; linux- > clk@vger.kernel.org; devicetree@vger.kernel.org; linux-arm- > kernel@lists.infradead.org; linux-kernel@vger.kernel.org > Subject: [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 > SoC > > Add missing G3D clock domain to Exynos850 SoC device tree. > > Signed-off-by: Sam Protsenko <semen.protsenko@linaro.org> Reviewed-by: Chanho Park <chanho61.park@samsung.com> > --- > arch/arm64/boot/dts/exynos/exynos850.dtsi | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/arch/arm64/boot/dts/exynos/exynos850.dtsi > b/arch/arm64/boot/dts/exynos/exynos850.dtsi > index a38fe5129937..d67e98120313 100644 > --- a/arch/arm64/boot/dts/exynos/exynos850.dtsi > +++ b/arch/arm64/boot/dts/exynos/exynos850.dtsi > @@ -245,6 +245,15 @@ cmu_peri: clock-controller@10030000 { > "dout_peri_uart", "dout_peri_ip"; > }; > > + cmu_g3d: clock-controller@11400000 { > + compatible = "samsung,exynos850-cmu-g3d"; > + reg = <0x11400000 0x8000>; > + #clock-cells = <1>; > + > + clocks = <&oscclk>, <&cmu_top CLK_DOUT_G3D_SWITCH>; > + clock-names = "oscclk", "dout_g3d_switch"; > + }; > + > cmu_apm: clock-controller@11800000 { > compatible = "samsung,exynos850-cmu-apm"; > reg = <0x11800000 0x8000>; > -- > 2.39.1 ^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2023-02-23 2:27 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2023-02-11 6:40 [PATCH 0/6] clk: samsung: exynos850: Add missing clocks for PM Sam Protsenko
2023-02-11 6:40 ` [PATCH 1/6] dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D Sam Protsenko
2023-02-14 23:56 ` Rob Herring
2023-02-11 6:40 ` [PATCH 2/6] dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks Sam Protsenko
2023-02-14 23:57 ` Rob Herring
2023-02-11 6:40 ` [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type Sam Protsenko
2023-02-11 6:40 ` [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain Sam Protsenko
2023-02-11 6:40 ` [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks Sam Protsenko
2023-02-11 6:40 ` [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC Sam Protsenko
[not found] ` <CGME20230211063955epcas2p177f52416ffb66cffa368fde02ee40411@epcms2p3>
2023-02-15 2:38 ` [PATCH 3/6] clk: samsung: clk-pll: Implement pll0818x PLL type CHANHO PARK
[not found] ` <CGME20230211063956epcas2p423cb99655dcfdb34c6847bb228aa7324@epcms2p2>
2023-02-15 2:40 ` [PATCH 5/6] clk: samsung: exynos850: Add AUD and HSI main gate clocks CHANHO PARK
2023-02-23 2:27 ` Sam Protsenko
[not found] ` <CGME20230211063957epcas2p2302d93ee2aeb2c5e680b771aa8bbc785@epcms2p4>
2023-02-15 3:24 ` [PATCH 4/6] clk: samsung: exynos850: Implement CMU_G3D domain CHANHO PARK
[not found] ` <CGME20230211063959epcas2p2500790b0402f151030ac65d405419649@epcms2p5>
2023-02-15 3:52 ` [PATCH 6/6] arm64: dts: exynos: Add CMU_G3D node for Exynos850 SoC CHANHO PARK
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