[PATCH V2 0/5] Add APSS clock controller support for IPQ9574

[PATCH V2 0/5] Add APSS clock controller support for IPQ9574

[Devi Priya]

APSS PLL found in IPQ9574 platform is of type Huayra.
This series adds support for the APSS clock to bump the CPU frequency
above 800MHz.

This series depends on the below patch set
https://lore.kernel.org/linux-arm-msm/20230217083308.12017-1-quic_kathirav@quicinc.com/

DTS patch depends on the PCIe series
https://lore.kernel.org/linux-arm-msm/20230214164135.17039-1-quic_devipriy@quicinc.com/

[V2]:
	- Reordered the patches as suggested
	- Dropped [PATCH 6/6] clk: qcom: Fix APSS PLL and RCG Configuration
	  as it was unrelated
	- Detailed Change logs are added to the respective patches
[V1]:
https://lore.kernel.org/linux-arm-kernel/20230113143647.14961-1-quic_devipriy@quicinc.com/

Devi Priya (5):
  dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible
  clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574
  dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC
  arm64: dts: qcom: ipq9574: Add support for APSS clock controller
  arm64: defconfig: Enable ipq6018 apss clock and PLL controller

 .../bindings/clock/qcom,a53pll.yaml           |  1 +
 .../mailbox/qcom,apcs-kpss-global.yaml        |  1 +
 arch/arm64/boot/dts/qcom/ipq9574.dtsi         | 18 ++++++++++++++++++
 arch/arm64/configs/defconfig                  |  1 +
 drivers/clk/qcom/apss-ipq-pll.c               | 19 +++++++++++++++++++
 5 files changed, 40 insertions(+)


base-commit: c068f40300a0eaa34f7105d137a5560b86951aa9
-- 
2.17.1

[PATCH V2 1/5] dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible

[Devi Priya]

IPQ9574 uses A73 PLL of type Huayra.
Add the IPQ9574 A73 compatible to A53 bindings as the PLL
properties match with that of A53

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- Dropped the qcom,a73pll.yaml and added the ipq9574
	  compatible to qcom,a53pll.yaml as suggested by konrad

 Documentation/devicetree/bindings/clock/qcom,a53pll.yaml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
index 3b6169f30154..476e81ad1a0c 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a53pll.yaml
@@ -19,6 +19,7 @@ properties:
       - qcom,ipq5332-a53pll
       - qcom,ipq6018-a53pll
       - qcom,ipq8074-a53pll
+      - qcom,ipq9574-a73pll
       - qcom,msm8916-a53pll
       - qcom,msm8939-a53pll
 
-- 
2.17.1

Re: [PATCH V2 1/5] dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible

[Krzysztof Kozlowski]

On 17/02/2023 14:41, Devi Priya wrote:
> IPQ9574 uses A73 PLL of type Huayra.
> Add the IPQ9574 A73 compatible to A53 bindings as the PLL
> properties match with that of A53
> 
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH V2 2/5] clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574

[Devi Priya]

Add the compatible and configuration values
for A73 Huayra PLL found on IPQ9574

Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- Rebased the changes on the below series which refactors the
	  driver to accommodate Huayra & Stromer Plus PLLs
	  https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
	- Changed the hex value in ipq9574_pll_config to lowercase
	- Dropped the mailbox driver changes as ipq9574 mailbox is 
	  compatible with ipq6018

 drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index cf4f0d340cbf..ce28d882ee78 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
 	.test_ctl_hi_val = 0x4000,
 };
 
+static const struct alpha_pll_config ipq9574_pll_config = {
+	.l = 0x3b,
+	.config_ctl_val = 0x200d4828,
+	.config_ctl_hi_val = 0x6,
+	.early_output_mask = BIT(3),
+	.aux2_output_mask = BIT(2),
+	.aux_output_mask = BIT(1),
+	.main_output_mask = BIT(0),
+	.test_ctl_val = 0x0,
+	.test_ctl_hi_val = 0x4000,
+};
+
 struct apss_pll_data {
 	int pll_type;
 	struct clk_alpha_pll *pll;
@@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
 	.pll_config = &ipq6018_pll_config,
 };
 
+static struct apss_pll_data ipq9574_pll_data = {
+	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
+	.pll = &ipq_pll_huayra,
+	.pll_config = &ipq9574_pll_config,
+};
+
 static const struct regmap_config ipq_pll_regmap_config = {
 	.reg_bits		= 32,
 	.reg_stride		= 4,
@@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
 	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
 	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
 	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
+	{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
-- 
2.17.1

Re: [PATCH V2 2/5] clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574

[Konrad Dybcio]

On 17.02.2023 14:41, Devi Priya wrote:
The subject is.. weird.. something like:

clk: qcom: apss-ipq-pll: add support for IPQ9574

would have made more sense, as you're not enabling the clock
driver, and certainly not *in* the SoC.

> Add the compatible and configuration values
Generally the lines in commit messages should be broken at 70-75
chars, not 40.

> for A73 Huayra PLL found on IPQ9574
> 
> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Is Praveenkumar's last name "I"?

> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
Otherwise the code looks good, I think.

Konrad
>  Changes in V2:
> 	- Rebased the changes on the below series which refactors the
> 	  driver to accommodate Huayra & Stromer Plus PLLs
> 	  https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
> 	- Changed the hex value in ipq9574_pll_config to lowercase
> 	- Dropped the mailbox driver changes as ipq9574 mailbox is 
> 	  compatible with ipq6018
> 
>  drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
>  1 file changed, 19 insertions(+)
> 
> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
> index cf4f0d340cbf..ce28d882ee78 100644
> --- a/drivers/clk/qcom/apss-ipq-pll.c
> +++ b/drivers/clk/qcom/apss-ipq-pll.c
> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
>  	.test_ctl_hi_val = 0x4000,
>  };
>  
> +static const struct alpha_pll_config ipq9574_pll_config = {
> +	.l = 0x3b,
> +	.config_ctl_val = 0x200d4828,
> +	.config_ctl_hi_val = 0x6,
> +	.early_output_mask = BIT(3),
> +	.aux2_output_mask = BIT(2),
> +	.aux_output_mask = BIT(1),
> +	.main_output_mask = BIT(0),
> +	.test_ctl_val = 0x0,
> +	.test_ctl_hi_val = 0x4000,
> +};
> +
>  struct apss_pll_data {
>  	int pll_type;
>  	struct clk_alpha_pll *pll;
> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
>  	.pll_config = &ipq6018_pll_config,
>  };
>  
> +static struct apss_pll_data ipq9574_pll_data = {
> +	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
> +	.pll = &ipq_pll_huayra,
> +	.pll_config = &ipq9574_pll_config,
> +};
> +
>  static const struct regmap_config ipq_pll_regmap_config = {
>  	.reg_bits		= 32,
>  	.reg_stride		= 4,
> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
>  	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
>  	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
>  	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
> +	{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
>  	{ }
>  };
>  MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);

Re: [PATCH V2 2/5] clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574

[Devi Priya]

On 2/17/2023 7:43 PM, Konrad Dybcio wrote:
> 
> 
> On 17.02.2023 14:41, Devi Priya wrote:
> The subject is.. weird.. something like:
> 
> clk: qcom: apss-ipq-pll: add support for IPQ9574
> 
> would have made more sense, as you're not enabling the clock
> driver, and certainly not *in* the SoC.
Yes agreed. Will update this in V3
> 
>> Add the compatible and configuration values
> Generally the lines in commit messages should be broken at 70-75
> chars, not 40.
> 
Okay
>> for A73 Huayra PLL found on IPQ9574
>>
>> Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
>> Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
> Is Praveenkumar's last name "I"?
yes, it is
> 
>> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
>> ---
> Otherwise the code looks good, I think.
Sure, thanks
> 
> Konrad
>>   Changes in V2:
>> 	- Rebased the changes on the below series which refactors the
>> 	  driver to accommodate Huayra & Stromer Plus PLLs
>> 	  https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
>> 	- Changed the hex value in ipq9574_pll_config to lowercase
>> 	- Dropped the mailbox driver changes as ipq9574 mailbox is
>> 	  compatible with ipq6018
>>
>>   drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
>>   1 file changed, 19 insertions(+)
>>
>> diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
>> index cf4f0d340cbf..ce28d882ee78 100644
>> --- a/drivers/clk/qcom/apss-ipq-pll.c
>> +++ b/drivers/clk/qcom/apss-ipq-pll.c
>> @@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
>>   	.test_ctl_hi_val = 0x4000,
>>   };
>>   
>> +static const struct alpha_pll_config ipq9574_pll_config = {
>> +	.l = 0x3b,
>> +	.config_ctl_val = 0x200d4828,
>> +	.config_ctl_hi_val = 0x6,
>> +	.early_output_mask = BIT(3),
>> +	.aux2_output_mask = BIT(2),
>> +	.aux_output_mask = BIT(1),
>> +	.main_output_mask = BIT(0),
>> +	.test_ctl_val = 0x0,
>> +	.test_ctl_hi_val = 0x4000,
>> +};
>> +
>>   struct apss_pll_data {
>>   	int pll_type;
>>   	struct clk_alpha_pll *pll;
>> @@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
>>   	.pll_config = &ipq6018_pll_config,
>>   };
>>   
>> +static struct apss_pll_data ipq9574_pll_data = {
>> +	.pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
>> +	.pll = &ipq_pll_huayra,
>> +	.pll_config = &ipq9574_pll_config,
>> +};
>> +
>>   static const struct regmap_config ipq_pll_regmap_config = {
>>   	.reg_bits		= 32,
>>   	.reg_stride		= 4,
>> @@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
>>   	{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
>>   	{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
>>   	{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
>> +	{ .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
>>   	{ }
>>   };
>>   MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
Best Regards,
Devi Priya

[PATCH V2 3/5] dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC

[Devi Priya]

Add the mailbox compatible for IPQ9574 SoC

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- Rebased the changes on the below patch set which adds fallback
	  support to ipq6018 compatible to avoid bloating the driver
          https://lore.kernel.org/linux-arm-msm/20230217083308.12017-5-quic_kathirav@quicinc.com/
	- Did not pick up the R-b tag as the changes were modified to
	  support the fallback mechanism

 .../devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml       | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
index 71195c0cadf9..dfb6a3453267 100644
--- a/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
+++ b/Documentation/devicetree/bindings/mailbox/qcom,apcs-kpss-global.yaml
@@ -19,6 +19,7 @@ properties:
       - items:
           - enum:
               - qcom,ipq5332-apcs-apps-global
+              - qcom,ipq9574-apcs-apps-global
           - const: qcom,ipq6018-apcs-apps-global
       - items:
           - enum:
-- 
2.17.1

Re: [PATCH V2 3/5] dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC

[Krzysztof Kozlowski]

On 17/02/2023 14:41, Devi Priya wrote:
> Add the mailbox compatible for IPQ9574 SoC
> 
> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
> ---
>  Changes in V2:

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Best regards,
Krzysztof

[PATCH V2 4/5] arm64: dts: qcom: ipq9574: Add support for APSS clock controller

[Devi Priya]

Add the APCS & A73 PLL nodes to support CPU frequency scaling

Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- No changes

 arch/arm64/boot/dts/qcom/ipq9574.dtsi | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/ipq9574.dtsi b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
index 70d920400265..d20f3c7383f5 100644
--- a/arch/arm64/boot/dts/qcom/ipq9574.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq9574.dtsi
@@ -405,6 +405,24 @@
 			};
 		};
 
+		apcs_glb: mailbox@b111000 {
+			compatible = "qcom,ipq9574-apcs-apps-global",
+				     "qcom,ipq6018-apcs-apps-global";
+			reg = <0x0b111000 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&a73pll>, <&xo_board_clk>;
+			clock-names = "pll", "xo";
+			#mbox-cells = <1>;
+		};
+
+		a73pll: clock@b116000 {
+			compatible = "qcom,ipq9574-a73pll";
+			reg = <0x0b116000 0x40>;
+			#clock-cells = <0>;
+			clocks = <&xo_board_clk>;
+			clock-names = "xo";
+		};
+
 		timer@b120000 {
 			compatible = "arm,armv7-timer-mem";
 			reg = <0x0b120000 0x1000>;
-- 
2.17.1

[PATCH V2 5/5] arm64: defconfig: Enable ipq6018 apss clock and PLL controller

[Devi Priya]

The PLL and IPQ6018 APSS clock controller are
used on several IPQ platforms to clock the CPU.
Hence it should be enabled and built-in.

Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
 Changes in V2:
	- Added the comment as why the config is being 
	  enabled

 arch/arm64/configs/defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig
index c2dfa833af3f..e5a797e3a4bf 100644
--- a/arch/arm64/configs/defconfig
+++ b/arch/arm64/configs/defconfig
@@ -1122,6 +1122,7 @@ CONFIG_QCOM_CLK_APCS_MSM8916=y
 CONFIG_QCOM_CLK_APCC_MSM8996=y
 CONFIG_QCOM_CLK_SMD_RPM=y
 CONFIG_QCOM_CLK_RPMH=y
+CONFIG_IPQ_APSS_6018=y
 CONFIG_IPQ_GCC_6018=y
 CONFIG_IPQ_GCC_8074=y
 CONFIG_IPQ_GCC_9574=y
-- 
2.17.1