From: Devi Priya <quic_devipriy@quicinc.com>
To: <agross@kernel.org>, <andersson@kernel.org>,
<konrad.dybcio@linaro.org>, <mturquette@baylibre.com>,
<sboyd@kernel.org>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <jassisinghbrar@gmail.com>,
<catalin.marinas@arm.com>, <will@kernel.org>,
<dmitry.baryshkov@linaro.org>, <arnd@arndb.de>,
<geert+renesas@glider.be>, <nfraprado@collabora.com>,
<broonie@kernel.org>, <rafal@milecki.pl>,
<linux-arm-msm@vger.kernel.org>, <linux-clk@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: <quic_srichara@quicinc.com>, <quic_gokulsri@quicinc.com>,
<quic_sjaganat@quicinc.com>, <quic_kathirav@quicinc.com>,
<quic_arajkuma@quicinc.com>, <quic_anusha@quicinc.com>
Subject: [PATCH V2 2/5] clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574
Date: Fri, 17 Feb 2023 19:11:04 +0530 [thread overview]
Message-ID: <20230217134107.13946-3-quic_devipriy@quicinc.com> (raw)
In-Reply-To: <20230217134107.13946-1-quic_devipriy@quicinc.com>
Add the compatible and configuration values
for A73 Huayra PLL found on IPQ9574
Co-developed-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Praveenkumar I <quic_ipkumar@quicinc.com>
Signed-off-by: Devi Priya <quic_devipriy@quicinc.com>
---
Changes in V2:
- Rebased the changes on the below series which refactors the
driver to accommodate Huayra & Stromer Plus PLLs
https://lore.kernel.org/linux-arm-msm/20230217083308.12017-2-quic_kathirav@quicinc.com/
- Changed the hex value in ipq9574_pll_config to lowercase
- Dropped the mailbox driver changes as ipq9574 mailbox is
compatible with ipq6018
drivers/clk/qcom/apss-ipq-pll.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/clk/qcom/apss-ipq-pll.c b/drivers/clk/qcom/apss-ipq-pll.c
index cf4f0d340cbf..ce28d882ee78 100644
--- a/drivers/clk/qcom/apss-ipq-pll.c
+++ b/drivers/clk/qcom/apss-ipq-pll.c
@@ -111,6 +111,18 @@ static const struct alpha_pll_config ipq8074_pll_config = {
.test_ctl_hi_val = 0x4000,
};
+static const struct alpha_pll_config ipq9574_pll_config = {
+ .l = 0x3b,
+ .config_ctl_val = 0x200d4828,
+ .config_ctl_hi_val = 0x6,
+ .early_output_mask = BIT(3),
+ .aux2_output_mask = BIT(2),
+ .aux_output_mask = BIT(1),
+ .main_output_mask = BIT(0),
+ .test_ctl_val = 0x0,
+ .test_ctl_hi_val = 0x4000,
+};
+
struct apss_pll_data {
int pll_type;
struct clk_alpha_pll *pll;
@@ -135,6 +147,12 @@ static struct apss_pll_data ipq6018_pll_data = {
.pll_config = &ipq6018_pll_config,
};
+static struct apss_pll_data ipq9574_pll_data = {
+ .pll_type = CLK_ALPHA_PLL_TYPE_HUAYRA,
+ .pll = &ipq_pll_huayra,
+ .pll_config = &ipq9574_pll_config,
+};
+
static const struct regmap_config ipq_pll_regmap_config = {
.reg_bits = 32,
.reg_stride = 4,
@@ -180,6 +198,7 @@ static const struct of_device_id apss_ipq_pll_match_table[] = {
{ .compatible = "qcom,ipq5332-a53pll", .data = &ipq5332_pll_data },
{ .compatible = "qcom,ipq6018-a53pll", .data = &ipq6018_pll_data },
{ .compatible = "qcom,ipq8074-a53pll", .data = &ipq8074_pll_data },
+ { .compatible = "qcom,ipq9574-a73pll", .data = &ipq9574_pll_data },
{ }
};
MODULE_DEVICE_TABLE(of, apss_ipq_pll_match_table);
--
2.17.1
next prev parent reply other threads:[~2023-02-17 13:42 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 13:41 [PATCH V2 0/5] Add APSS clock controller support for IPQ9574 Devi Priya
2023-02-17 13:41 ` [PATCH V2 1/5] dt-bindings: clock: qcom,a53pll: add IPQ9574 compatible Devi Priya
2023-02-18 10:21 ` Krzysztof Kozlowski
2023-02-17 13:41 ` Devi Priya [this message]
2023-02-17 14:13 ` [PATCH V2 2/5] clk: qcom: apss-ipq-pll: Enable APSS clock driver in IPQ9574 Konrad Dybcio
2023-02-20 13:55 ` Devi Priya
2023-02-17 13:41 ` [PATCH V2 3/5] dt-bindings: mailbox: qcom: add compatible for IPQ9574 SoC Devi Priya
2023-02-18 10:22 ` Krzysztof Kozlowski
2023-02-17 13:41 ` [PATCH V2 4/5] arm64: dts: qcom: ipq9574: Add support for APSS clock controller Devi Priya
2023-02-17 13:41 ` [PATCH V2 5/5] arm64: defconfig: Enable ipq6018 apss clock and PLL controller Devi Priya
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