From: Conor Dooley <conor@kernel.org>
To: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>
Cc: conor@kernel.org, "Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <sboyd@kernel.org>,
"Thomas Gleixner" <tglx@linutronix.de>,
"Marc Zyngier" <maz@kernel.org>,
"Thierry Reding" <thierry.reding@gmail.com>,
"Uwe Kleine-König" <u.kleine-koenig@pengutronix.de>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-pwm@vger.kernel.org,
"Conor Dooley" <conor.dooley@microchip.com>,
"Sagar Kadam" <sagar.kadam@openfive.com>,
"Sagar Kadam" <sagar.kadam@sifive.com>
Subject: [PATCH] dt-bindings: drop Sagar Kadam from SiFive binding maintainership
Date: Fri, 17 Feb 2023 18:00:36 +0000 [thread overview]
Message-ID: <20230217180035.39658-1-conor@kernel.org> (raw)
From: Conor Dooley <conor.dooley@microchip.com>
Sagar's email listed in maintainers is bouncing as his division was sold
off by the company. I attempted to contact him some days ago on what the
bounce email told me was his new contact information, but am yet to
receive a response.
Paul and Palmer are listed on each of the bindings, both of whom were
alive & well as of Wednesday so the bindings remain maintained.
CC: Sagar Kadam <sagar.kadam@openfive.com>
CC: Sagar Kadam <sagar.kadam@sifive.com>
Link: https://lore.kernel.org/all/785425ca-4000-a7e4-16d6-4d68c91b158d@kernel.org/
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Palmer/Paul, as mentioned Wednesday, here you go!
---
Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml | 1 -
.../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 -
Documentation/devicetree/bindings/pwm/pwm-sifive.yaml | 1 -
Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml | 3 +--
4 files changed, 1 insertion(+), 5 deletions(-)
diff --git a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
index c3be1b600007..c79e752283aa 100644
--- a/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
+++ b/Documentation/devicetree/bindings/clock/sifive/fu540-prci.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive FU540 Power Reset Clock Interrupt Controller (PRCI)
maintainers:
- - Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
index 99e01f4d0a69..63bc89e13480 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml
@@ -45,7 +45,6 @@ description:
from S-mode. So add thead,c900-plic to distinguish them.
maintainers:
- - Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
- Palmer Dabbelt <palmer@dabbelt.com>
diff --git a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
index 605c1766dba8..bae993128981 100644
--- a/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
+++ b/Documentation/devicetree/bindings/pwm/pwm-sifive.yaml
@@ -8,7 +8,6 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive PWM controller
maintainers:
- - Sagar Kadam <sagar.kadam@sifive.com>
- Paul Walmsley <paul.walmsley@sifive.com>
description:
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
index bf3f07421f7e..0551a0d1b3df 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
@@ -8,8 +8,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
maintainers:
- - Sagar Kadam <sagar.kadam@sifive.com>
- - Paul Walmsley <paul.walmsley@sifive.com>
+ - Paul Walmsley <paul.walmsley@sifive.com>
description:
The SiFive Composable Cache Controller is used to provide access to fast copies
--
2.39.1
next reply other threads:[~2023-02-17 18:01 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-17 18:00 Conor Dooley [this message]
2023-02-18 18:33 ` [PATCH] dt-bindings: drop Sagar Kadam from SiFive binding maintainership Palmer Dabbelt
2023-02-21 15:39 ` Rob Herring
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