Re: [PATCH 00/16] Qcom: Fix PCI I/O range defined in devicetree

[Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>]

On Tue, Feb 28, 2023 at 05:58:37PM +0100, Arnd Bergmann wrote:
> On Tue, Feb 28, 2023, at 17:47, Manivannan Sadhasivam wrote:
> > Hi,
> >
> > This series fixes the issue with PCI I/O ranges defined in devicetree of
> > Qualcomm SoCs as reported by Arnd [1]. Most of the Qualcomm SoCs define
> > identical mapping for the PCI I/O range. But the PCI device I/O ports
> > are usually located between 0x0 to 64KiB/1MiB. So the defined PCI addresses are
> > mostly bogus. The lack of bug report on this issue indicates that no one really
> > tested legacy PCI devices with these SoCs.
> >
> > This series also contains a couple of cleanup patches that aligns the entries of
> > ranges property.
> 
> Looks good to me. I already commented that we may also want to use
> 64KB everywhere instead of 1MB for the per-host window size.

I also spotted this discrepancy while working on this series, but the size
seems to be not universal across SoCs from many vendors. So I settled with
whatever range that was used before.

>  Regardless of that, please add
> 
> Reviewed-by: Arnd Bergmann <arnd@arndb.de>
> 
> I would also prefer to do this in fewer patches, maybe one to
> change all the prefixes, and another one to change the location,
> or whichever way Bjorn prefers.
> 

Well, the only intention of doing a per-patch change is to backport them if
needed. But I'll defer it to Bjorn.

Thanks,
Mani

>      Arnd

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