[PATCH v2 0/3] Add JH7110 USB driver support

[PATCH v2 0/3] Add JH7110 USB driver support

[Minda Chen]

This patchset adds USB driver for the StarFive JH7110 SoC.
USB work mode is peripheral and using USB 2.0 PHY in VisionFive 2 board.
The patch has been tested on the VisionFive 2 board.

This patchset should be applied after the patchset [1] and patch [2]:
[1] https://lore.kernel.org/all/20230221083323.302471-1-xingyu.wu@starfivetech.com/
[2] https://lore.kernel.org/all/20230215113249.47727-4-william.qiu@starfivetech.com/

This patchset is base on v6.3-rc1

patch 1 is usb phy dt-binding document.
patch 2 is the glue layer of Cadence USB3 and USB phy setting. USB controller IP is Cadence USB3.
patch 3 is USB device tree configuration.

previous version
---
v1: https://patchwork.kernel.org/project/linux-usb/patch/20230306095339.26006-1-minda.chen@starfivetech.com/

changes
v2
  1. (patch 1) dt-binding check test pass and no warning. The document example is the same as dts config.
  2. (patch 2) using dev_err_probe and syscon_regmap_lookup_by_phandle_args function. Some formats changes
  3. (patch 3) dts nodes sorted by the address after @

Minda Chen (3):
  dt-bindings: phy: Add StarFive JH7110 USB dt-binding
  usb: cdns3: add StarFive JH7110 USB glue layer
  dts: usb: add StarFive JH7110 USB dts configuration.

 .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++
 MAINTAINERS                                   |   7 +
 .../jh7110-starfive-visionfive-2.dtsi         |   6 +
 arch/riscv/boot/dts/starfive/jh7110.dtsi      |  38 ++
 drivers/usb/cdns3/Kconfig                     |  11 +
 drivers/usb/cdns3/Makefile                    |   1 +
 drivers/usb/cdns3/cdns3-starfive.c            | 374 ++++++++++++++++++
 7 files changed, 595 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c


base-commit: 8ca09d5fa3549d142c2080a72a4c70ce389163cd
prerequisite-patch-id: 0e6d1df3ba9aecd925a0c604b9d91f7143be88ca
prerequisite-patch-id: ac150a8c622e858e088df8121093d448df49c245
prerequisite-patch-id: 044263ef2fb9f1e5a586edbf85d5f67814a28430
prerequisite-patch-id: 74390c129b92fb35a7088e2e5c869632c4cb3d06
prerequisite-patch-id: de93ebec041625e940f195403069b46ec17fc99c
prerequisite-patch-id: 1b2d0982b18da060c82134f05bf3ce16425bac8d
prerequisite-patch-id: 090ba4b78d47bc19204916e76fdbc70021785388
prerequisite-patch-id: a5d9e0f7d4f8163f566678894cf693015119f2d9
prerequisite-patch-id: f01a78c30f6f1970b4db7758c339bd4e5c882b16
prerequisite-patch-id: 417736eb958e1158c60a5ed74bc2350394321a80
prerequisite-patch-id: ff9fe0b043a5f7f74a1f6af5cebc4793c6f14ce7
prerequisite-patch-id: 290602062703e666191c20ca02f2840471a6bf4f
prerequisite-patch-id: f0b29adbb18edffbfeec7292c5f33e2bbeb30945
prerequisite-patch-id: 258ea5f9b8bf41b6981345dcc81795f25865d38f
prerequisite-patch-id: 8b6f2c9660c0ac0ee4e73e4c21aca8e6b75e81b9
prerequisite-patch-id: dbb0c0151b8bdf093e6ce79fd2fe3f60791a6e0b
prerequisite-patch-id: ea9a6d0313dd3936c8de0239dc2072c3360a2f6b
prerequisite-patch-id: d57e95d31686772abc4c4d5aa1cadc344dc293cd
prerequisite-patch-id: 27197d69922ad1f33a193dfe0a8cc2b27d67982d
prerequisite-patch-id: f9ce88e490c2473c3c94ad63fa26bc91829ce2cc
prerequisite-patch-id: 7acbc9c924e802712d3574dd74a6b3576089f78c
prerequisite-patch-id: b9b8fda5e8cd2dd4c9101ec03f4c8fb8e8caa573
prerequisite-patch-id: 63a6de4511f1a7ae974551e7097af9bb91db1b0d
prerequisite-patch-id: aaff99c0bdd1604048d0713b44084ad4604816e1
-- 
2.17.1

[PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Minda Chen]

Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
USB controller is cadence USB 3.0 IP.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
 1 file changed, 158 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml

diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
new file mode 100644
index 000000000000..daa88d065deb
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
@@ -0,0 +1,158 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive USB 2.0 and 3.0 PHY
+
+maintainers:
+  - Minda Chen<minda.chen@starfivetech.com>
+
+properties:
+  compatible:
+    items:
+      - const: starfive,jh7110-usb
+
+  reg:
+    maxItems: 2
+
+  reg-names:
+    items:
+      - const: usb3
+      - const: usb2
+
+  clocks:
+    items:
+      - description: usb 125m clock
+      - description: app 125m clock
+      - description: lpm clock
+      - description: stb clock
+      - description: apb clock
+      - description: axi clock
+      - description: utmi apb clock
+
+  clock-names:
+    items:
+      - const: usb_125m
+      - const: usb0_app_125
+      - const: usb0_lpm
+      - const: usb0_stb
+      - const: usb0_apb
+      - const: usb0_axi
+      - const: usb0_utmi_apb
+
+  resets:
+    items:
+      - description: USB0_PWRUP reset
+      - description: USB0_APB reset
+      - description: USB0_AXI reset
+      - description: USB0_UTMI_APB reset
+
+  starfive,sys-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle to System Register Controller sys_syscon node.
+        - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
+    description:
+      The phandle to System Register Controller syscon node and the offset
+      of SYS_SYSCONSAIF__SYSCFG register for USB.
+
+  starfive,stg-syscon:
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    items:
+      items:
+        - description: phandle to System Register Controller stg_syscon node.
+        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
+    description:
+      The phandle to System Register Controller syscon node and the offset
+      of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
+      for USB.
+
+  dr_mode:
+    description: PHY mode.
+    enum:
+      - host
+      - peripheral
+      - otg
+
+  "#address-cells":
+    maximum: 2
+
+  "#size-cells":
+    maximum: 2
+
+  ranges: true
+
+  starfive,usb2-only:
+    type: boolean
+    description: Set USB using usb 2.0 phy. Supprt USB 2.0 only
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - starfive,sys-syscon
+  - starfive,stg-syscon
+  - dr_mode
+  - "#address-cells"
+  - "#size-cells"
+  - ranges
+
+patternProperties:
+  "^usb@[0-9a-f]+$":
+    type: object
+    description: |
+      usbphy node should have '1' usb controller subnode.
+      It could be Cadence USB3 DRD controller.
+      Cadence USB3 should follow the bindings specified in
+      Documentation/devicetree/bindings/usb/cdns,usb3.yaml
+
+additionalProperties: false
+
+examples:
+  - |
+    usbphy@10200000 {
+      compatible = "starfive,jh7110-usb";
+      reg = <0x10210000 0x1000>,
+            <0x10200000 0x1000>;
+      reg-names = "usb3", "usb2";
+      clocks = <&syscrg 95>,
+               <&stgcrg 6>,
+               <&stgcrg 4>,
+               <&stgcrg 5>,
+               <&stgcrg 1>,
+               <&stgcrg 3>,
+               <&stgcrg 2>;
+      clock-names = "usb_125m", "usb0_app_125", "usb0_lpm",
+                    "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb";
+      resets = <&stgcrg 10>,
+               <&stgcrg 8>,
+               <&stgcrg 7>,
+               <&stgcrg 9>;
+      starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
+      starfive,sys-syscon = <&sys_syscon 0x18>;
+      dr_mode = "host";
+      #address-cells = <1>;
+      #size-cells = <1>;
+      ranges;
+
+      usb@10100000 {
+        compatible = "cdns,usb3";
+        reg = <0x10100000 0x10000>,
+              <0x10110000 0x10000>,
+              <0x10120000 0x10000>;
+        reg-names = "otg", "xhci", "dev";
+        interrupts = <100>, <108>, <110>;
+        interrupt-names = "host", "peripheral", "otg";
+        phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+        maximum-speed = "super-speed";
+      };
+    };
-- 
2.17.1

[PATCH v2 2/3] usb: cdns3: add StarFive JH7110 USB glue layer

[Minda Chen]

There is a Cadence USB3 core for JH7110 SoCs, the cdns
core is the child for this glue layer device.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 MAINTAINERS                        |   7 +
 drivers/usb/cdns3/Kconfig          |  11 +
 drivers/usb/cdns3/Makefile         |   1 +
 drivers/usb/cdns3/cdns3-starfive.c | 374 +++++++++++++++++++++++++++++
 4 files changed, 393 insertions(+)
 create mode 100644 drivers/usb/cdns3/cdns3-starfive.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 47a3dd16b59b..20a64fa39a14 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -19970,6 +19970,13 @@ M:	William Qiu <william.qiu@starfivetech.com>
 S:	Supported
 F:	Documentation/devicetree/bindings/soc/starfive/jh7110-syscon.yaml
 
+STARFIVE JH71X0 USB PHY DRIVERS
+M:	Emil Renner Berthing <kernel@esmil.dk>
+M:	Minda Chen <minda.chen@starfivetech.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/phy/starfive,jh7110-usb*.yaml
+F:	drivers/usb/cdns3/cdns3-starfive.c
+
 STATIC BRANCH/CALL
 M:	Peter Zijlstra <peterz@infradead.org>
 M:	Josh Poimboeuf <jpoimboe@kernel.org>
diff --git a/drivers/usb/cdns3/Kconfig b/drivers/usb/cdns3/Kconfig
index b98ca0a1352a..0a514b591527 100644
--- a/drivers/usb/cdns3/Kconfig
+++ b/drivers/usb/cdns3/Kconfig
@@ -78,6 +78,17 @@ config USB_CDNS3_IMX
 
 	  For example, imx8qm and imx8qxp.
 
+config USB_CDNS3_STARFIVE
+	tristate "Cadence USB3 support on StarFive SoC platforms"
+	depends on ARCH_STARFIVE || COMPILE_TEST
+	help
+	  Say 'Y' or 'M' here if you are building for StarFive SoCs
+	  platforms that contain Cadence USB3 controller core.
+
+	  e.g. JH7110.
+
+	  If you choose to build this driver as module it will
+	  be dynamically linked and module will be called cdns3-starfive.ko
 endif
 
 if USB_CDNS_SUPPORT
diff --git a/drivers/usb/cdns3/Makefile b/drivers/usb/cdns3/Makefile
index 61edb2f89276..48dfae75b5aa 100644
--- a/drivers/usb/cdns3/Makefile
+++ b/drivers/usb/cdns3/Makefile
@@ -24,6 +24,7 @@ endif
 obj-$(CONFIG_USB_CDNS3_PCI_WRAP)		+= cdns3-pci-wrap.o
 obj-$(CONFIG_USB_CDNS3_TI)			+= cdns3-ti.o
 obj-$(CONFIG_USB_CDNS3_IMX)			+= cdns3-imx.o
+obj-$(CONFIG_USB_CDNS3_STARFIVE)		+= cdns3-starfive.o
 
 cdnsp-udc-pci-y					:= cdnsp-pci.o
 
diff --git a/drivers/usb/cdns3/cdns3-starfive.c b/drivers/usb/cdns3/cdns3-starfive.c
new file mode 100644
index 000000000000..9b80be29ac0d
--- /dev/null
+++ b/drivers/usb/cdns3/cdns3-starfive.c
@@ -0,0 +1,374 @@
+// SPDX-License-Identifier: GPL-2.0
+/**
+ * cdns3-starfive.c - StarFive specific Glue layer for Cadence USB Controller
+ *
+ * Copyright (C) 2022 Starfive, Inc.
+ * Author:	Yanhong Wang <yanhong.wang@starfivetech.com>
+ * Author:	Mason Huo <mason.huo@starfivetech.com>
+ * Author:	Minda Chen <minda.chen@starfivetech.com>
+ */
+
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/module.h>
+#include <linux/mfd/syscon.h>
+#include <linux/kernel.h>
+#include <linux/platform_device.h>
+#include <linux/io.h>
+#include <linux/of_platform.h>
+#include <linux/regmap.h>
+#include <linux/reset.h>
+#include <linux/usb/otg.h>
+#include "core.h"
+
+#define USB_STRAP_HOST			BIT(17)
+#define USB_STRAP_DEVICE		BIT(18)
+#define USB_STRAP_MASK			GENMASK(18, 16)
+
+#define USB_SUSPENDM_HOST		BIT(19)
+#define USB_SUSPENDM_DEVICE		(0 << 19)
+#define USB_SUSPENDM_MASK		BIT(19)
+
+#define USB_SUSPENDM_BYPS		BIT(20)
+#define USB_REFCLK_MODE			BIT(23)
+#define USB_PLL_EN			BIT(22)
+#define USB_PDRSTN_SPLIT		BIT(17)
+
+#define PCIE_CKREF_SRC_MASK		GENMASK(19, 18)
+#define PCIE_CLK_SEL_MASK		GENMASK(21, 20)
+#define PCIE_PHY_MODE			BIT(20)
+#define PCIE_PHY_MODE_MASK		GENMASK(21, 20)
+#define PCIE_USB3_BUS_WIDTH_MASK	GENMASK(3, 2)
+#define PCIE_USB3_RATE_MASK		GENMASK(6, 5)
+#define PCIE_USB3_RX_STANDBY_MASK	BIT(7)
+#define PCIE_USB3_PHY_ENABLE		BIT(4)
+#define PCIE_USB3_PHY_PLL_CTL_OFF	(0x1f * 4)
+
+#define USB_125M_CLK_RATE		125000000
+
+#define USB_LS_KEEPALIVE_OFF		0x4
+#define USB_LS_KEEPALIVE_ENABLE		BIT(4)
+
+#define USB3_DOWN_SS_MODE		BIT(4)
+
+struct cdns_starfive {
+	struct device *dev;
+	struct regmap *stg_syscon;
+	struct regmap *sys_syscon;
+	struct reset_control *resets;
+	struct clk_bulk_data *clks;
+	int num_clks;
+	struct clk *usb_125m_clk;
+	u32 sys_offset;
+	u32 stg_offset_4;
+	u32 stg_offset_196;
+	u32 stg_offset_328;
+	u32 stg_offset_500;
+	bool usb2_only;
+	enum usb_dr_mode mode;
+	void __iomem *phybase_20;
+	void __iomem *phybase_30;
+};
+
+static int cdns_mode_init(struct platform_device *pdev,
+				struct cdns_starfive *data)
+{
+	enum usb_dr_mode mode;
+
+	/* Init usb 2.0 utmi phy */
+	regmap_update_bits(data->stg_syscon, data->stg_offset_4,
+		USB_SUSPENDM_BYPS, USB_SUSPENDM_BYPS);
+	regmap_update_bits(data->stg_syscon, data->stg_offset_4,
+		USB_PLL_EN, USB_PLL_EN);
+	regmap_update_bits(data->stg_syscon, data->stg_offset_4,
+		USB_REFCLK_MODE, USB_REFCLK_MODE);
+
+	if (data->usb2_only) {
+		/* Disconnect usb 3.0 phy mode */
+		regmap_update_bits(data->sys_syscon, data->sys_offset,
+			USB_PDRSTN_SPLIT, USB_PDRSTN_SPLIT);
+	} else {
+		/* Config usb 3.0 pipe phy */
+		regmap_update_bits(data->stg_syscon, data->stg_offset_196,
+			PCIE_CKREF_SRC_MASK, 0);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_196,
+			PCIE_CLK_SEL_MASK, 0);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_328,
+			PCIE_PHY_MODE_MASK, PCIE_PHY_MODE);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_500,
+			PCIE_USB3_BUS_WIDTH_MASK, 0);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_500,
+			PCIE_USB3_RATE_MASK, 0);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_500,
+			PCIE_USB3_RX_STANDBY_MASK, 0);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_500,
+			PCIE_USB3_PHY_ENABLE, PCIE_USB3_PHY_ENABLE);
+
+		/* Connect usb 3.0 phy mode */
+		regmap_update_bits(data->sys_syscon, data->sys_offset,
+			USB_PDRSTN_SPLIT, 0);
+	}
+	mode = usb_get_dr_mode(&pdev->dev);
+	data->mode = mode;
+
+	switch (mode) {
+	case USB_DR_MODE_HOST:
+		regmap_update_bits(data->stg_syscon,
+			data->stg_offset_4,
+			USB_STRAP_MASK,
+			USB_STRAP_HOST);
+		regmap_update_bits(data->stg_syscon,
+			data->stg_offset_4,
+			USB_SUSPENDM_MASK,
+			USB_SUSPENDM_HOST);
+		break;
+
+	case USB_DR_MODE_PERIPHERAL:
+		regmap_update_bits(data->stg_syscon, data->stg_offset_4,
+			USB_STRAP_MASK, USB_STRAP_DEVICE);
+		regmap_update_bits(data->stg_syscon, data->stg_offset_4,
+			USB_SUSPENDM_MASK, USB_SUSPENDM_DEVICE);
+		break;
+
+	case USB_DR_MODE_UNKNOWN:
+	case USB_DR_MODE_OTG:
+	default:
+		break;
+	}
+
+	return 0;
+}
+
+static int cdns_clk_rst_init(struct cdns_starfive *data)
+{
+	int ret;
+
+	data->usb_125m_clk = devm_clk_get(data->dev, "usb_125m");
+	if (IS_ERR(data->usb_125m_clk))
+		return dev_err_probe(data->dev, PTR_ERR(data->usb_125m_clk),
+			"Failed to get 125m clock\n");
+
+	data->num_clks = devm_clk_bulk_get_all(data->dev, &data->clks);
+	if (data->num_clks < 0)
+		return dev_err_probe(data->dev, -ENODEV,
+			"Failed to get clocks\n");
+
+	/* Needs to set the USB_125M clock explicitly,
+	 * since it's divided from pll0 clock, and the pll0 clock
+	 * changes per the cpu frequency.
+	 */
+	ret = clk_set_rate(data->usb_125m_clk, USB_125M_CLK_RATE);
+	if (ret)
+		return dev_err_probe(data->dev, ret,
+			"Failed to set 125m clocks\n");
+
+	ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+	if (ret)
+		return dev_err_probe(data->dev, ret,
+			"failed to enable clocks\n");
+
+	data->resets = devm_reset_control_array_get_exclusive(data->dev);
+	if (IS_ERR(data->resets)) {
+		ret = dev_err_probe(data->dev, PTR_ERR(data->resets),
+			"Failed to get resets");
+		goto err_clk_init;
+	}
+
+	ret = reset_control_deassert(data->resets);
+	if (ret) {
+		ret = dev_err_probe(data->dev, ret,
+			"failed to reset clocks\n");
+		goto err_clk_init;
+	}
+
+	return ret;
+
+err_clk_init:
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+	return ret;
+}
+
+static void cdns_starfive_set_phy(struct cdns_starfive *data)
+{
+	unsigned int val;
+
+	if (data->mode != USB_DR_MODE_PERIPHERAL) {
+		/* Enable the LS speed keep-alive signal */
+		val = readl(data->phybase_20 + USB_LS_KEEPALIVE_OFF);
+		val |= USB_LS_KEEPALIVE_ENABLE;
+		writel(val, data->phybase_20 + USB_LS_KEEPALIVE_OFF);
+	}
+
+	/* Configuare spread-spectrum mode: down-spread-spectrum */
+	if (!data->usb2_only)
+		writel(USB3_DOWN_SS_MODE, data->phybase_30 + PCIE_USB3_PHY_PLL_CTL_OFF);
+}
+
+static int cdns_starfive_phy_init(struct platform_device *pdev,
+							struct cdns_starfive *data)
+{
+	struct device *dev = &pdev->dev;
+
+	data->phybase_20 = devm_platform_ioremap_resource_byname(pdev, "usb2");
+	if (IS_ERR(data->phybase_20))
+		return dev_err_probe(dev, PTR_ERR(data->phybase_20),
+			"Can't map phybase_20 IOMEM resource\n");
+
+	data->phybase_30 = devm_platform_ioremap_resource_byname(pdev, "usb3");
+	if (IS_ERR(data->phybase_30))
+		return dev_err_probe(dev, PTR_ERR(data->phybase_30),
+			"Can't map phybase_30 IOMEM resource\n");
+
+	cdns_starfive_set_phy(data);
+
+	return 0;
+}
+
+static int cdns_starfive_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct device_node *node = pdev->dev.of_node;
+	struct cdns_starfive *data;
+	unsigned int args[4];
+	int ret;
+
+	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
+	if (!data)
+		return -ENOMEM;
+
+	platform_set_drvdata(pdev, data);
+
+	data->dev = dev;
+
+	data->usb2_only = device_property_read_bool(dev, "starfive,usb2-only");
+	data->stg_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+		"starfive,stg-syscon", 4, args);
+
+	if (IS_ERR(data->stg_syscon))
+		return dev_err_probe(dev, PTR_ERR(data->stg_syscon),
+			"Failed to parse starfive,stg-syscon\n");
+
+	data->stg_offset_4 = args[0];
+	data->stg_offset_196 = args[1];
+	data->stg_offset_328 = args[2];
+	data->stg_offset_500 = args[3];
+
+	data->sys_syscon = syscon_regmap_lookup_by_phandle_args(pdev->dev.of_node,
+		"starfive,sys-syscon", 1, args);
+	if (IS_ERR(data->sys_syscon))
+		return dev_err_probe(dev, PTR_ERR(data->sys_syscon),
+			"Failed to parse starfive,sys-syscon\n");
+
+	data->sys_offset = args[0];
+
+	cdns_mode_init(pdev, data);
+
+	ret = cdns_clk_rst_init(data);
+	if (ret)
+		return ret;
+
+	ret = cdns_starfive_phy_init(pdev, data);
+	if (ret)
+		return ret;
+
+	ret = of_platform_populate(node, NULL, NULL, dev);
+	if (ret)
+		return dev_err_probe(dev, ret, "Failed to create children\n");
+
+	device_set_wakeup_capable(dev, true);
+	pm_runtime_set_active(dev);
+	pm_runtime_enable(dev);
+
+	dev_info(dev, "usb mode %d %s probe success\n",
+		data->mode, data->usb2_only ? "2.0" : "3.0");
+
+	return 0;
+}
+
+static int cdns_starfive_remove_core(struct device *dev, void *c)
+{
+	struct platform_device *pdev = to_platform_device(dev);
+
+	platform_device_unregister(pdev);
+
+	return 0;
+}
+
+static int cdns_starfive_remove(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	pm_runtime_get_sync(dev);
+	device_for_each_child(dev, NULL, cdns_starfive_remove_core);
+
+	reset_control_assert(data->resets);
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+	pm_runtime_disable(dev);
+	pm_runtime_put_noidle(dev);
+	platform_set_drvdata(pdev, NULL);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int cdns_starfive_resume(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+	int ret;
+
+	ret = clk_set_rate(data->usb_125m_clk, USB_125M_CLK_RATE);
+	if (ret)
+		return ret;
+
+	ret = clk_bulk_prepare_enable(data->num_clks, data->clks);
+	if (ret)
+		return ret;
+
+	ret = reset_control_deassert(data->resets);
+	if (ret)
+		return ret;
+
+	cdns_starfive_set_phy(data);
+
+	return 0;
+}
+
+static int cdns_starfive_suspend(struct device *dev)
+{
+	struct cdns_starfive *data = dev_get_drvdata(dev);
+
+	clk_bulk_disable_unprepare(data->num_clks, data->clks);
+	reset_control_assert(data->resets);
+
+	return 0;
+}
+#endif
+
+static const struct dev_pm_ops cdns_starfive_pm_ops = {
+	SET_RUNTIME_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume, NULL)
+	SET_SYSTEM_SLEEP_PM_OPS(cdns_starfive_suspend, cdns_starfive_resume)
+};
+
+static const struct of_device_id cdns_starfive_of_match[] = {
+	{ .compatible = "starfive,jh7110-usb", },
+	{ /* sentinel */ }
+};
+MODULE_DEVICE_TABLE(of, cdns_starfive_of_match);
+
+static struct platform_driver cdns_starfive_driver = {
+	.probe		= cdns_starfive_probe,
+	.remove		= cdns_starfive_remove,
+	.driver		= {
+		.name	= "cdns3-starfive",
+		.of_match_table	= cdns_starfive_of_match,
+		.pm	= &cdns_starfive_pm_ops,
+	},
+};
+module_platform_driver(cdns_starfive_driver);
+
+MODULE_ALIAS("platform:cdns3-starfive");
+MODULE_AUTHOR("YanHong Wang <yanhong.wang@starfivetech.com>");
+MODULE_AUTHOR("Mason Huo <mason.huo@starfivetech.com>");
+MODULE_LICENSE("GPL v2");
+MODULE_DESCRIPTION("Cadence USB3 StarFive Glue Layer");
-- 
2.17.1

[PATCH v2 3/3] dts: usb: add StarFive JH7110 USB dts configuration.

[Minda Chen]

USB phy dts configuration. Also includes Cadence USB
subnode configuration.

Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
---
 .../jh7110-starfive-visionfive-2.dtsi         |  6 +++
 arch/riscv/boot/dts/starfive/jh7110.dtsi      | 38 +++++++++++++++++++
 2 files changed, 44 insertions(+)

diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
index f144c3254213..933750ce753d 100644
--- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
@@ -236,3 +236,9 @@
 		};
 	};
 };
+
+&usb0 {
+	starfive,usb2-only;
+	dr_mode = "peripheral";
+	status = "okay";
+};
diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
index c29f8dd9e557..fa622e18dc0e 100644
--- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
@@ -362,6 +362,44 @@
 			status = "disabled";
 		};
 
+		usb0: usbphy@10200000 {
+			compatible = "starfive,jh7110-usb";
+			reg = <0x0 0x10210000 0x0 0x1000>,
+			      <0x0 0x10200000 0x0 0x1000>;
+			reg-names = "usb3", "usb2";
+			clocks = <&syscrg JH7110_SYSCLK_USB_125M>,
+				 <&stgcrg JH7110_STGCLK_USB0_APP_125>,
+				 <&stgcrg JH7110_STGCLK_USB0_LPM>,
+				 <&stgcrg JH7110_STGCLK_USB0_STB>,
+				 <&stgcrg JH7110_STGCLK_USB0_APB>,
+				 <&stgcrg JH7110_STGCLK_USB0_AXI>,
+				 <&stgcrg JH7110_STGCLK_USB0_UTMI_APB>;
+			clock-names = "usb_125m", "usb0_app_125", "usb0_lpm",
+				"usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb";
+			resets = <&stgcrg JH7110_STGRST_USB0_PWRUP>,
+				 <&stgcrg JH7110_STGRST_USB0_APB>,
+				 <&stgcrg JH7110_STGRST_USB0_AXI>,
+				 <&stgcrg JH7110_STGRST_USB0_UTMI_APB>;
+			starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
+			starfive,sys-syscon = <&sys_syscon 0x18>;
+			status = "disabled";
+			#address-cells = <2>;
+			#size-cells = <2>;
+			ranges;
+
+			usbdrd_cdns3: usb@10100000 {
+				compatible = "cdns,usb3";
+				reg = <0x0 0x10100000 0x0 0x10000>,
+				      <0x0 0x10110000 0x0 0x10000>,
+				      <0x0 0x10120000 0x0 0x10000>;
+				reg-names = "otg", "xhci", "dev";
+				interrupts = <100>, <108>, <110>;
+				interrupt-names = "host", "peripheral", "otg";
+				phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
+				maximum-speed = "super-speed";
+			};
+		};
+
 		stgcrg: clock-controller@10230000 {
 			compatible = "starfive,jh7110-stgcrg";
 			reg = <0x0 0x10230000 0x0 0x10000>;
-- 
2.17.1

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Rob Herring]

On Wed, 08 Mar 2023 16:27:58 +0800, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
> USB controller is cadence USB 3.0 IP.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>  1 file changed, 158 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:

dtschema/dtc warnings/errors:
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.example.dtb: usb@10100000: phy-names:1: 'anyOf' conditional failed, one must be fixed:
	'cdns3,usb2-phy' was expected
	'cdns3,usb3-phy' was expected
	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/usb/cdns,usb3.yaml
/builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.example.dtb: usb@10100000: 'phys' is a dependency of 'phy-names'
	From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/phy/phy-consumer.yaml

doc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230308082800.3008-2-minda.chen@starfivetech.com

The base for the series is generally the latest rc1. A different dependency
should be noted in *this* patch.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit after running the above command yourself. Note
that DT_SCHEMA_FILES can be set to your schema file to speed up checking
your schema. However, it must be unset to test all examples with your schema.

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Rob Herring]

On Wed, Mar 08, 2023 at 04:27:58PM +0800, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
> USB controller is cadence USB 3.0 IP.
> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>  1 file changed, 158 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> new file mode 100644
> index 000000000000..daa88d065deb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml

Filename should match the compatible. The filename seems more correct 
than the compatible...

> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive USB 2.0 and 3.0 PHY
> +
> +maintainers:
> +  - Minda Chen<minda.chen@starfivetech.com>
> +
> +properties:
> +  compatible:
> +    items:
> +      - const: starfive,jh7110-usb

What's the USB controller called?

> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: usb3
> +      - const: usb2
> +
> +  clocks:
> +    items:
> +      - description: usb 125m clock
> +      - description: app 125m clock
> +      - description: lpm clock
> +      - description: stb clock
> +      - description: apb clock
> +      - description: axi clock
> +      - description: utmi apb clock
> +
> +  clock-names:
> +    items:
> +      - const: usb_125m
> +      - const: usb0_app_125
> +      - const: usb0_lpm
> +      - const: usb0_stb
> +      - const: usb0_apb
> +      - const: usb0_axi
> +      - const: usb0_utmi_apb

usb_ and usb0_ is redundant, drop.

> +
> +  resets:
> +    items:
> +      - description: USB0_PWRUP reset
> +      - description: USB0_APB reset
> +      - description: USB0_AXI reset
> +      - description: USB0_UTMI_APB reset
> +
> +  starfive,sys-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:

Are there multiple entries of phandle+offset because this says there 
are. You want '- items:' here to limit it to 1 phandle+offset.

> +        - description: phandle to System Register Controller sys_syscon node.
> +        - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
> +    description:
> +      The phandle to System Register Controller syscon node and the offset
> +      of SYS_SYSCONSAIF__SYSCFG register for USB.
> +
> +  starfive,stg-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:

Same here.

> +        - description: phandle to System Register Controller stg_syscon node.
> +        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +    description:
> +      The phandle to System Register Controller syscon node and the offset
> +      of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
> +      for USB.
> +
> +  dr_mode:

Usually this belongs in the controller node.

> +    description: PHY mode.
> +    enum:
> +      - host
> +      - peripheral
> +      - otg
> +
> +  "#address-cells":
> +    maximum: 2
> +
> +  "#size-cells":
> +    maximum: 2
> +
> +  ranges: true
> +
> +  starfive,usb2-only:
> +    type: boolean
> +    description: Set USB using usb 2.0 phy. Supprt USB 2.0 only

The 'maximum-speed' property in the controller should be enough. Why is 
this needed.

Being a PHY, you are missing #phy-cells.

> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - resets
> +  - starfive,sys-syscon
> +  - starfive,stg-syscon
> +  - dr_mode
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +patternProperties:
> +  "^usb@[0-9a-f]+$":
> +    type: object
> +    description: |
> +      usbphy node should have '1' usb controller subnode.
> +      It could be Cadence USB3 DRD controller.
> +      Cadence USB3 should follow the bindings specified in
> +      Documentation/devicetree/bindings/usb/cdns,usb3.yaml

Why is the controller a child of the phy?

> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    usbphy@10200000 {
> +      compatible = "starfive,jh7110-usb";
> +      reg = <0x10210000 0x1000>,
> +            <0x10200000 0x1000>;
> +      reg-names = "usb3", "usb2";
> +      clocks = <&syscrg 95>,
> +               <&stgcrg 6>,
> +               <&stgcrg 4>,
> +               <&stgcrg 5>,
> +               <&stgcrg 1>,
> +               <&stgcrg 3>,
> +               <&stgcrg 2>;
> +      clock-names = "usb_125m", "usb0_app_125", "usb0_lpm",
> +                    "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb";
> +      resets = <&stgcrg 10>,
> +               <&stgcrg 8>,
> +               <&stgcrg 7>,
> +               <&stgcrg 9>;
> +      starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
> +      starfive,sys-syscon = <&sys_syscon 0x18>;
> +      dr_mode = "host";
> +      #address-cells = <1>;
> +      #size-cells = <1>;
> +      ranges;
> +
> +      usb@10100000 {
> +        compatible = "cdns,usb3";

This needs a platform specific compatible.

> +        reg = <0x10100000 0x10000>,
> +              <0x10110000 0x10000>,
> +              <0x10120000 0x10000>;
> +        reg-names = "otg", "xhci", "dev";
> +        interrupts = <100>, <108>, <110>;
> +        interrupt-names = "host", "peripheral", "otg";
> +        phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
> +        maximum-speed = "super-speed";
> +      };
> +    };
> -- 
> 2.17.1
> 

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Minda Chen]

On 2023/3/8 22:06, Rob Herring wrote:
> 
> On Wed, 08 Mar 2023 16:27:58 +0800, Minda Chen wrote:
>> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
>> USB controller is cadence USB 3.0 IP.
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>>  1 file changed, 158 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> 
> 
> My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
> on your patch (DT_CHECKER_FLAGS is new in v5.13):
> 
> yamllint warnings/errors:
> 
> dtschema/dtc warnings/errors:
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.example.dtb: usb@10100000: phy-names:1: 'anyOf' conditional failed, one must be fixed:
> 	'cdns3,usb2-phy' was expected
> 	'cdns3,usb3-phy' was expected
> 	From schema: /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/usb/cdns,usb3.yaml
> /builds/robherring/dt-review-ci/linux/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.example.dtb: usb@10100000: 'phys' is a dependency of 'phy-names'
> 	From schema: /usr/local/lib/python3.10/dist-packages/dtschema/schemas/phy/phy-consumer.yaml
> 
> doc reference errors (make refcheckdocs):
> 
> See https://patchwork.ozlabs.org/project/devicetree-bindings/patch/20230308082800.3008-2-minda.chen@starfivetech.com
> 
> The base for the series is generally the latest rc1. A different dependency
> should be noted in *this* patch.
> 
> If you already ran 'make dt_binding_check' and didn't see the above
> error(s), then make sure 'yamllint' is installed and dt-schema is up to
> date:
> 
> pip3 install dtschema --upgrade
> 
> Please check and re-submit after running the above command yourself. Note
> that DT_SCHEMA_FILES can be set to your schema file to speed up checking
> your schema. However, it must be unset to test all examples with your schema.
> 
I am sorry about this, I just run dtbs_check, not dt_binding_check. Next version I will fix it. 

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Minda Chen]

On 2023/3/9 2:12, Rob Herring wrote:
> On Wed, Mar 08, 2023 at 04:27:58PM +0800, Minda Chen wrote:
>> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
>> USB controller is cadence USB 3.0 IP.
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>>  1 file changed, 158 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> new file mode 100644
>> index 000000000000..daa88d065deb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> 
> Filename should match the compatible. The filename seems more correct 
> than the compatible...
> 
[1] jh7110 USB dts configure is similar to  Documentation/devicetree/bindings/usb/ti,j721e-usb.yaml
But we have PHY (10200000). So I will add  Documentation/devicetree/bindings/usb/starfive,jh7110-usb.yaml
as a wrap level.
starfive,jh7110-usb-phy.yaml contains only phy setting.
>> @@ -0,0 +1,158 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive USB 2.0 and 3.0 PHY
>> +
>> +maintainers:
>> +  - Minda Chen<minda.chen@starfivetech.com>
>> +
>> +properties:
>> +  compatible:
>> +    items:
>> +      - const: starfive,jh7110-usb
> 
> What's the USB controller called?
> 
I will change to "starfive,jh7110-usb-phy"
>> +
>> +  reg:
>> +    maxItems: 2
>> +
>> +  reg-names:
>> +    items:
>> +      - const: usb3
>> +      - const: usb2
>> +
>> +  clocks:
>> +    items:
>> +      - description: usb 125m clock
>> +      - description: app 125m clock
>> +      - description: lpm clock
>> +      - description: stb clock
>> +      - description: apb clock
>> +      - description: axi clock
>> +      - description: utmi apb clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: usb_125m
>> +      - const: usb0_app_125
>> +      - const: usb0_lpm
>> +      - const: usb0_stb
>> +      - const: usb0_apb
>> +      - const: usb0_axi
>> +      - const: usb0_utmi_apb
> 
> usb_ and usb0_ is redundant, drop.
> 
ok
>> +
>> +  resets:
>> +    items:
>> +      - description: USB0_PWRUP reset
>> +      - description: USB0_APB reset
>> +      - description: USB0_AXI reset
>> +      - description: USB0_UTMI_APB reset
>> +
>> +  starfive,sys-syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      items:
> 
ok
> Are there multiple entries of phandle+offset because this says there 
> are. You want '- items:' here to limit it to 1 phandle+offset.
> 
>> +        - description: phandle to System Register Controller sys_syscon node.
>> +        - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
>> +    description:
>> +      The phandle to System Register Controller syscon node and the offset
>> +      of SYS_SYSCONSAIF__SYSCFG register for USB.
>> +
>> +  starfive,stg-syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      items:
> 
> Same here.
> 
ok
>> +        - description: phandle to System Register Controller stg_syscon node.
>> +        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +    description:
>> +      The phandle to System Register Controller syscon node and the offset
>> +      of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
>> +      for USB.
>> +
>> +  dr_mode:
> 
> Usually this belongs in the controller node.
> 
cdns3 usb controller IP default set to host mode. If cdns3 usb controller "dr_mode"
set to "peripheral", cdns3 controller can't be registered.

in driver/usb/cdns3/core.c
132         } else if (cdns->dr_mode != dr_mode) {
133                 dev_err(dev, "Incorrect DRD configuration\n");
134                 return -EINVAL;
135         }


If dr_mode is not set in int wrap level, peripheral mode can not be work.

And I see other USB PHY contain dr-mode setting.
>> +    description: PHY mode.
>> +    enum:
>> +      - host
>> +      - peripheral
>> +      - otg
>> +
>> +  "#address-cells":
>> +    maximum: 2
>> +
>> +  "#size-cells":
>> +    maximum: 2
>> +
>> +  ranges: true
>> +
>> +  starfive,usb2-only:
>> +    type: boolean
>> +    description: Set USB using usb 2.0 phy. Supprt USB 2.0 only
> 
> The 'maximum-speed' property in the controller should be enough. Why is 
> this needed.
> 
maybe I can delete this setting.
> Being a PHY, you are missing #phy-cells.
> 
ok
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
>> +  - resets
>> +  - starfive,sys-syscon
>> +  - starfive,stg-syscon
>> +  - dr_mode
>> +  - "#address-cells"
>> +  - "#size-cells"
>> +  - ranges
>> +
>> +patternProperties:
>> +  "^usb@[0-9a-f]+$":
>> +    type: object
>> +    description: |
>> +      usbphy node should have '1' usb controller subnode.
>> +      It could be Cadence USB3 DRD controller.
>> +      Cadence USB3 should follow the bindings specified in
>> +      Documentation/devicetree/bindings/usb/cdns,usb3.yaml
> 
> Why is the controller a child of the phy?
> 
same as [1]. I will change this .
>> +
>> +additionalProperties: false
>> +
>> +examples:
>> +  - |
>> +    usbphy@10200000 {
>> +      compatible = "starfive,jh7110-usb";
>> +      reg = <0x10210000 0x1000>,
>> +            <0x10200000 0x1000>;
>> +      reg-names = "usb3", "usb2";
>> +      clocks = <&syscrg 95>,
>> +               <&stgcrg 6>,
>> +               <&stgcrg 4>,
>> +               <&stgcrg 5>,
>> +               <&stgcrg 1>,
>> +               <&stgcrg 3>,
>> +               <&stgcrg 2>;
>> +      clock-names = "usb_125m", "usb0_app_125", "usb0_lpm",
>> +                    "usb0_stb", "usb0_apb", "usb0_axi", "usb0_utmi_apb";
>> +      resets = <&stgcrg 10>,
>> +               <&stgcrg 8>,
>> +               <&stgcrg 7>,
>> +               <&stgcrg 9>;
>> +      starfive,stg-syscon = <&stg_syscon 0x4 0xc4 0x148 0x1f4>;
>> +      starfive,sys-syscon = <&sys_syscon 0x18>;
>> +      dr_mode = "host";
>> +      #address-cells = <1>;
>> +      #size-cells = <1>;
>> +      ranges;
>> +
>> +      usb@10100000 {
>> +        compatible = "cdns,usb3";
> 
> This needs a platform specific compatible.
> 
same as [1]
>> +        reg = <0x10100000 0x10000>,
>> +              <0x10110000 0x10000>,
>> +              <0x10120000 0x10000>;
>> +        reg-names = "otg", "xhci", "dev";
>> +        interrupts = <100>, <108>, <110>;
>> +        interrupt-names = "host", "peripheral", "otg";
>> +        phy-names = "cdns3,usb3-phy", "cnds3,usb2-phy";
>> +        maximum-speed = "super-speed";
>> +      };
>> +    };
>> -- 
>> 2.17.1
>> 

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Krzysztof Kozlowski]

On 08/03/2023 09:27, Minda Chen wrote:
> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
> USB controller is cadence USB 3.0 IP.

Subject: drop second/last, redundant "binding". The "dt-bindings" prefix
is already stating that these are bindings.

> 
> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> ---
>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>  1 file changed, 158 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> 
> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> new file mode 100644
> index 000000000000..daa88d065deb
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
> @@ -0,0 +1,158 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: StarFive USB 2.0 and 3.0 PHY
> +
> +maintainers:
> +  - Minda Chen<minda.chen@starfivetech.com>

Missing space

> +
> +properties:
> +  compatible:
> +    items:

Drop items, it's just one item.


> +      - const: starfive,jh7110-usb
> +
> +  reg:
> +    maxItems: 2
> +
> +  reg-names:
> +    items:
> +      - const: usb3
> +      - const: usb2
> +
> +  clocks:
> +    items:
> +      - description: usb 125m clock
> +      - description: app 125m clock
> +      - description: lpm clock
> +      - description: stb clock
> +      - description: apb clock
> +      - description: axi clock
> +      - description: utmi apb clock
> +
> +  clock-names:
> +    items:
> +      - const: usb_125m
> +      - const: usb0_app_125
> +      - const: usb0_lpm
> +      - const: usb0_stb
> +      - const: usb0_apb
> +      - const: usb0_axi
> +      - const: usb0_utmi_apb
> +
> +  resets:
> +    items:
> +      - description: USB0_PWRUP reset
> +      - description: USB0_APB reset
> +      - description: USB0_AXI reset
> +      - description: USB0_UTMI_APB reset
> +
> +  starfive,sys-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:
> +        - description: phandle to System Register Controller sys_syscon node.
> +        - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
> +    description:
> +      The phandle to System Register Controller syscon node and the offset
> +      of SYS_SYSCONSAIF__SYSCFG register for USB.
> +
> +  starfive,stg-syscon:
> +    $ref: /schemas/types.yaml#/definitions/phandle-array
> +    items:
> +      items:
> +        - description: phandle to System Register Controller stg_syscon node.
> +        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
> +    description:
> +      The phandle to System Register Controller syscon node and the offset
> +      of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
> +      for USB.
> +
> +  dr_mode:
> +    description: PHY mode.
> +    enum:
> +      - host
> +      - peripheral
> +      - otg
> +
> +  "#address-cells":
> +    maximum: 2
> +
> +  "#size-cells":
> +    maximum: 2
> +
> +  ranges: true
> +
> +  starfive,usb2-only:
> +    type: boolean
> +    description: Set USB using usb 2.0 phy. Supprt USB 2.0 only
> +
> +required:
> +  - compatible
> +  - reg
> +  - reg-names
> +  - clocks
> +  - clock-names
> +  - resets
> +  - starfive,sys-syscon
> +  - starfive,stg-syscon
> +  - dr_mode
> +  - "#address-cells"
> +  - "#size-cells"
> +  - ranges
> +
> +patternProperties:

This goes before required block

> +  "^usb@[0-9a-f]+$":
> +    type: object
> +    description: |
> +      usbphy node should have '1' usb controller subnode.
> +      It could be Cadence USB3 DRD controller.
> +      Cadence USB3 should follow the bindings specified in
> +      Documentation/devicetree/bindings/usb/cdns,usb3.yaml

$ref instead of free form text


Best regards,
Krzysztof

Re: [PATCH v2 1/3] dt-bindings: phy: Add StarFive JH7110 USB dt-binding

[Minda Chen]

On 2023/3/9 18:07, Krzysztof Kozlowski wrote:
> On 08/03/2023 09:27, Minda Chen wrote:
>> Add StarFive JH7110 SoC USB 3.0 phy dt-binding.
>> USB controller is cadence USB 3.0 IP.
> 
> Subject: drop second/last, redundant "binding". The "dt-bindings" prefix
> is already stating that these are bindings.
> 
>> 
>> Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
>> ---
>>  .../bindings/phy/starfive,jh7110-usb-phy.yaml | 158 ++++++++++++++++++
>>  1 file changed, 158 insertions(+)
>>  create mode 100644 Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> 
>> diff --git a/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> new file mode 100644
>> index 000000000000..daa88d065deb
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/phy/starfive,jh7110-usb-phy.yaml
>> @@ -0,0 +1,158 @@
>> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/phy/starfive,jh7110-usb-phy.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: StarFive USB 2.0 and 3.0 PHY
>> +
>> +maintainers:
>> +  - Minda Chen<minda.chen@starfivetech.com>
> 
> Missing space
> 
>> +
>> +properties:
>> +  compatible:
>> +    items:
> 
> Drop items, it's just one item.
> 
> 
>> +      - const: starfive,jh7110-usb
>> +
>> +  reg:
>> +    maxItems: 2
>> +
>> +  reg-names:
>> +    items:
>> +      - const: usb3
>> +      - const: usb2
>> +
>> +  clocks:
>> +    items:
>> +      - description: usb 125m clock
>> +      - description: app 125m clock
>> +      - description: lpm clock
>> +      - description: stb clock
>> +      - description: apb clock
>> +      - description: axi clock
>> +      - description: utmi apb clock
>> +
>> +  clock-names:
>> +    items:
>> +      - const: usb_125m
>> +      - const: usb0_app_125
>> +      - const: usb0_lpm
>> +      - const: usb0_stb
>> +      - const: usb0_apb
>> +      - const: usb0_axi
>> +      - const: usb0_utmi_apb
>> +
>> +  resets:
>> +    items:
>> +      - description: USB0_PWRUP reset
>> +      - description: USB0_APB reset
>> +      - description: USB0_AXI reset
>> +      - description: USB0_UTMI_APB reset
>> +
>> +  starfive,sys-syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      items:
>> +        - description: phandle to System Register Controller sys_syscon node.
>> +        - description: offset of SYS_SYSCONSAIF__SYSCFG register for USB.
>> +    description:
>> +      The phandle to System Register Controller syscon node and the offset
>> +      of SYS_SYSCONSAIF__SYSCFG register for USB.
>> +
>> +  starfive,stg-syscon:
>> +    $ref: /schemas/types.yaml#/definitions/phandle-array
>> +    items:
>> +      items:
>> +        - description: phandle to System Register Controller stg_syscon node.
>> +        - description: register0 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register1 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register2 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +        - description: register3 offset of STG_SYSCONSAIF__SYSCFG register for USB.
>> +    description:
>> +      The phandle to System Register Controller syscon node and the offset
>> +      of STG_SYSCONSAIF__SYSCFG register for USB. Total 4 regsisters offset
>> +      for USB.
>> +
>> +  dr_mode:
>> +    description: PHY mode.
>> +    enum:
>> +      - host
>> +      - peripheral
>> +      - otg
>> +
>> +  "#address-cells":
>> +    maximum: 2
>> +
>> +  "#size-cells":
>> +    maximum: 2
>> +
>> +  ranges: true
>> +
>> +  starfive,usb2-only:
>> +    type: boolean
>> +    description: Set USB using usb 2.0 phy. Supprt USB 2.0 only
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - clocks
>> +  - clock-names
>> +  - resets
>> +  - starfive,sys-syscon
>> +  - starfive,stg-syscon
>> +  - dr_mode
>> +  - "#address-cells"
>> +  - "#size-cells"
>> +  - ranges
>> +
>> +patternProperties:
> 
> This goes before required block
> 
>> +  "^usb@[0-9a-f]+$":
>> +    type: object
>> +    description: |
>> +      usbphy node should have '1' usb controller subnode.
>> +      It could be Cadence USB3 DRD controller.
>> +      Cadence USB3 should follow the bindings specified in
>> +      Documentation/devicetree/bindings/usb/cdns,usb3.yaml
> 
> $ref instead of free form text
> 
> 
ok, thanks. Next version I will follow the comments to change.
> Best regards,
> Krzysztof
>