* [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 14:33 ` Krzysztof Kozlowski
2023-03-08 12:52 ` [PATCH v1 02/25] arm64: dts: colibri-imx8x: Update spdx license Philippe Schenker
` (23 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Toradex sells the Colibri iMX8X module in variants with the i.MX 8QXP
and i.MX8DX SoC. Prepare for this by moving majority of stuff from
imx8qxp-colibri.dtsi into imx8x-colibri.dtsi.
Remove DX from the model string.
This commit intends no functional change.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../dts/freescale/imx8qxp-colibri-eval-v3.dts | 4 +-
.../boot/dts/freescale/imx8qxp-colibri.dtsi | 590 +----------------
...val-v3.dtsi => imx8x-colibri-eval-v3.dtsi} | 0
.../boot/dts/freescale/imx8x-colibri.dtsi | 593 ++++++++++++++++++
4 files changed, 597 insertions(+), 590 deletions(-)
rename arch/arm64/boot/dts/freescale/{imx8qxp-colibri-eval-v3.dtsi => imx8x-colibri-eval-v3.dtsi} (100%)
create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
index 6b21a295c126..413a9e9d6c28 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
@@ -6,10 +6,10 @@
/dts-v1/;
#include "imx8qxp-colibri.dtsi"
-#include "imx8qxp-colibri-eval-v3.dtsi"
+#include "imx8x-colibri-eval-v3.dtsi"
/ {
- model = "Toradex Colibri iMX8QXP/DX on Colibri Evaluation Board V3";
+ model = "Toradex Colibri iMX8QXP on Colibri Evaluation Board V3";
compatible = "toradex,colibri-imx8x-eval-v3",
"toradex,colibri-imx8x", "fsl,imx8qxp";
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 89d70e030433..1ffc42f4a4b3 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -4,595 +4,9 @@
*/
#include "imx8qxp.dtsi"
+#include "imx8x-colibri.dtsi"
/ {
- model = "Toradex Colibri iMX8QXP/DX Module";
+ model = "Toradex Colibri iMX8QXP Module";
compatible = "toradex,colibri-imx8x", "fsl,imx8qxp";
-
- chosen {
- stdout-path = &lpuart3;
- };
-
- reg_module_3v3: regulator-module-3v3 {
- compatible = "regulator-fixed";
- regulator-name = "+V3.3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-};
-
-/* On-module I2C */
-&i2c0 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
- status = "okay";
-
- /* Touch controller */
- touchscreen@2c {
- compatible = "adi,ad7879-1";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ad7879_int>;
- reg = <0x2c>;
- interrupt-parent = <&lsio_gpio3>;
- interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-max-pressure = <4096>;
- adi,resistance-plate-x = <120>;
- adi,first-conversion-delay = /bits/ 8 <3>;
- adi,acquisition-time = /bits/ 8 <1>;
- adi,median-filter-size = /bits/ 8 <2>;
- adi,averaging = /bits/ 8 <1>;
- adi,conversion-interval = /bits/ 8 <255>;
- };
-};
-
-/* Colibri I2C */
-&i2c1 {
- #address-cells = <1>;
- #size-cells = <0>;
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_i2c1>;
-};
-
-/* Colibri UART_B */
-&lpuart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart0>;
-};
-
-/* Colibri UART_C */
-&lpuart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart2>;
-};
-
-/* Colibri UART_A */
-&lpuart3 {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
-};
-
-/* Colibri FastEthernet */
-&fec1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec1>;
- pinctrl-1 = <&pinctrl_fec1_sleep>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
- fsl,magic-packet;
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@2 {
- compatible = "ethernet-phy-ieee802.3-c22";
- max-speed = <100>;
- reg = <2>;
- };
- };
-};
-
-/* On-module eMMC */
-&usdhc1 {
- bus-width = <8>;
- non-removable;
- no-sd;
- no-sdio;
- pinctrl-names = "default", "state_100mhz", "state_200mhz";
- pinctrl-0 = <&pinctrl_usdhc1>;
- pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
- pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
- status = "okay";
-};
-
-/* Colibri SD/MMC Card */
-&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_module_3v3>;
- pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
- pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
- pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
- pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
- disable-wp;
-};
-
-&iomuxc {
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
-
- /* On-module touch pen-down interrupt */
- pinctrl_ad7879_int: ad7879intgrp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21
- >;
- };
-
- /* Colibri Analogue Inputs */
- pinctrl_adc0: adc0grp {
- fsl,pins = <
- IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */
- IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */
- IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */
- IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */
- >;
- };
-
- pinctrl_can_int: canintgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */
- >;
- };
-
- pinctrl_csi_ctl: csictlgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */
- IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */
- >;
- };
-
- pinctrl_ext_io0: extio0grp {
- fsl,pins = <
- IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */
- >;
- };
-
- /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
- pinctrl_fec1: fec1grp {
- fsl,pins = <
- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
- >;
- };
-
- pinctrl_fec1_sleep: fec1slpgrp {
- fsl,pins = <
- IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
- IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
- IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
- IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
- IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
- IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
- IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
- IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
- IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
- IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
- >;
- };
-
- /* Colibri optional CAN on UART_B RTS/CTS */
- pinctrl_flexcan1: flexcan0grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
- IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
- >;
- };
-
- /* Colibri optional CAN on PS2 */
- pinctrl_flexcan2: flexcan1grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
- IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
- >;
- };
-
- /* Colibri optional CAN on UART_A TXD/RXD */
- pinctrl_flexcan3: flexcan2grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
- IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
- >;
- };
-
- /* Colibri LCD Back-Light GPIO */
- pinctrl_gpio_bl_on: gpioblongrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */
- >;
- };
-
- pinctrl_gpiokeys: gpiokeysgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
- >;
- };
-
- pinctrl_hog0: hog0grp {
- fsl,pins = <
- IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
- IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
- IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
- IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
- IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
- IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
- IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
- IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
- IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
- IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
- IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
- IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
- IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
- IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
- IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
- IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
- IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
- IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
- IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
- IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
- IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
- IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
- IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
- IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
- IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
- IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
- >;
- };
-
- pinctrl_hog1: hog1grp {
- fsl,pins = <
- IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */
- IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
- >;
- };
-
- /*
- * This pin is used in the SCFW as a UART. Using it from
- * Linux would require rewritting the SCFW board file.
- */
- pinctrl_hog_scfw: hogscfwgrp {
- fsl,pins = <
- IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */
- >;
- };
-
- /* On Module I2C */
- pinctrl_i2c0: i2c0grp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
- IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
- >;
- };
-
- /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
- pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */
- IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */
- >;
- };
-
- /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
- pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */
- IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */
- >;
- };
-
- /* Colibri I2C */
- pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */
- IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
- >;
- };
-
- /* Colibri Parallel RGB LCD Interface */
- pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
- IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
- IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
- IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
- IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
- IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
- IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
- IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
- IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
- IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */
- IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */
- IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
- IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
- IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
- IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
- IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
- IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
- IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
- IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
- IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
- IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
- IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
- IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
- IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
- >;
- };
-
- /* Colibri SPI */
- pinctrl_lpspi2: lpspi2grp {
- fsl,pins = <
- IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
- >;
- };
-
- /* Colibri UART_B */
- pinctrl_lpuart0: lpuart0grp {
- fsl,pins = <
- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
- IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
- IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
- >;
- };
-
- /* Colibri UART_C */
- pinctrl_lpuart2: lpuart2grp {
- fsl,pins = <
- IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */
- IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */
- >;
- };
-
- /* Colibri UART_A */
- pinctrl_lpuart3: lpuart3grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */
- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
- >;
- };
-
- /* Colibri UART_A Control */
- pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
- IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
- IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
- IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
- IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
- IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
- >;
- };
-
- /* On module wifi module */
- pinctrl_pcieb: pciebgrp {
- fsl,pins = <
- IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
- IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
- IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
- >;
- };
-
- /* Colibri PWM_A */
- pinctrl_pwm_a: pwmagrp {
- /* both pins are connected together, reserve the unused CSI_D05 */
- fsl,pins = <
- IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */
- IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */
- >;
- };
-
- /* Colibri PWM_B */
- pinctrl_pwm_b: pwmbgrp {
- fsl,pins = <
- IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */
- >;
- };
-
- /* Colibri PWM_C */
- pinctrl_pwm_c: pwmcgrp {
- fsl,pins = <
- IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */
- >;
- };
-
- /* Colibri PWM_D */
- pinctrl_pwm_d: pwmdgrp {
- /* both pins are connected together, reserve the unused CSI_D04 */
- fsl,pins = <
- IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */
- IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
- >;
- };
-
- /* On-module I2S */
- pinctrl_sai0: sai0grp {
- fsl,pins = <
- IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
- IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
- IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
- IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
- >;
- };
-
- /* Colibri Audio Analogue Microphone GND */
- pinctrl_sgtl5000: sgtl5000grp {
- fsl,pins = <
- /* MIC GND EN */
- IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41
- >;
- };
-
- /* On-module SGTL5000 clock */
- pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
- fsl,pins = <
- IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21
- >;
- };
-
- /* On-module USB interrupt */
- pinctrl_usb3503a: usb3503agrp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61
- >;
- };
-
- /* Colibri USB Client Cable Detect */
- pinctrl_usbc_det: usbcdetgrp {
- fsl,pins = <
- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */
- >;
- };
-
- /* USB Host Power Enable */
- pinctrl_usbh1_reg: usbh1reggrp {
- fsl,pins = <
- IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */
- >;
- };
-
- /* On-module eMMC */
- pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- >;
- };
-
- pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- >;
- };
-
- pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- >;
- };
-
- /* Colibri SD/MMC Card Detect */
- pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */
- >;
- };
-
- pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */
- >;
- };
-
- /* Colibri SD/MMC Card */
- pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
- };
-
- pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
- };
-
- pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
- };
-
- pinctrl_usdhc2_sleep: usdhc2slpgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
- };
-
- pinctrl_wifi: wifigrp {
- fsl,pins = <
- IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
- >;
- };
};
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
similarity index 100%
rename from arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dtsi
rename to arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
new file mode 100644
index 000000000000..cb22bde19ea0
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -0,0 +1,593 @@
+// SPDX-License-Identifier: GPL-2.0+ OR MIT
+/*
+ * Copyright 2019 Toradex
+ */
+
+/ {
+ chosen {
+ stdout-path = &lpuart3;
+ };
+
+ reg_module_3v3: regulator-module-3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "+V3.3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+};
+
+/* On-module I2C */
+&i2c0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
+ status = "okay";
+
+ /* Touch controller */
+ touchscreen@2c {
+ compatible = "adi,ad7879-1";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ad7879_int>;
+ reg = <0x2c>;
+ interrupt-parent = <&lsio_gpio3>;
+ interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
+ touchscreen-max-pressure = <4096>;
+ adi,resistance-plate-x = <120>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,acquisition-time = /bits/ 8 <1>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,averaging = /bits/ 8 <1>;
+ adi,conversion-interval = /bits/ 8 <255>;
+ };
+};
+
+/* Colibri I2C */
+&i2c1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_i2c1>;
+};
+
+/* Colibri UART_B */
+&lpuart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart0>;
+};
+
+/* Colibri UART_C */
+&lpuart2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart2>;
+};
+
+/* Colibri UART_A */
+&lpuart3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
+};
+
+/* Colibri FastEthernet */
+&fec1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+ phy-mode = "rmii";
+ phy-handle = <ðphy0>;
+ fsl,magic-packet;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ max-speed = <100>;
+ reg = <2>;
+ };
+ };
+};
+
+/* On-module eMMC */
+&usdhc1 {
+ bus-width = <8>;
+ non-removable;
+ no-sd;
+ no-sdio;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz";
+ pinctrl-0 = <&pinctrl_usdhc1>;
+ pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
+ pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ status = "okay";
+};
+
+/* Colibri SD/MMC Card */
+&usdhc2 {
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
+ vmmc-supply = <®_module_3v3>;
+ pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
+ pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
+ pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ disable-wp;
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
+
+ /* On-module touch pen-down interrupt */
+ pinctrl_ad7879_int: ad7879intgrp {
+ fsl,pins = <
+ IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21
+ >;
+ };
+
+ /* Colibri Analogue Inputs */
+ pinctrl_adc0: adc0grp {
+ fsl,pins = <
+ IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */
+ IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */
+ IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */
+ IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */
+ >;
+ };
+
+ pinctrl_can_int: canintgrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */
+ >;
+ };
+
+ pinctrl_csi_ctl: csictlgrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */
+ IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */
+ >;
+ };
+
+ pinctrl_ext_io0: extio0grp {
+ fsl,pins = <
+ IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */
+ >;
+ };
+
+ /* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
+ pinctrl_fec1: fec1grp {
+ fsl,pins = <
+ IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
+ IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
+ IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
+ IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
+ IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
+ IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
+ >;
+ };
+
+ pinctrl_fec1_sleep: fec1slpgrp {
+ fsl,pins = <
+ IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
+ IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
+ IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
+ IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
+ IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
+ IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
+ IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
+ IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
+ IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
+ IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
+ >;
+ };
+
+ /* Colibri optional CAN on UART_B RTS/CTS */
+ pinctrl_flexcan1: flexcan0grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
+ IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
+ >;
+ };
+
+ /* Colibri optional CAN on PS2 */
+ pinctrl_flexcan2: flexcan1grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
+ IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
+ >;
+ };
+
+ /* Colibri optional CAN on UART_A TXD/RXD */
+ pinctrl_flexcan3: flexcan2grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
+ IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
+ >;
+ };
+
+ /* Colibri LCD Back-Light GPIO */
+ pinctrl_gpio_bl_on: gpioblongrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */
+ >;
+ };
+
+ pinctrl_gpiokeys: gpiokeysgrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
+ >;
+ };
+
+ pinctrl_hog0: hog0grp {
+ fsl,pins = <
+ IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
+ IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
+ IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
+ IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
+ IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
+ IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
+ IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
+ IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
+ IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
+ IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
+ IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
+ IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
+ IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
+ IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
+ IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
+ IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
+ IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
+ IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
+ IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
+ IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
+ IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
+ IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
+ IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
+ IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
+ IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
+ IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
+ >;
+ };
+
+ pinctrl_hog1: hog1grp {
+ fsl,pins = <
+ IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */
+ IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
+ >;
+ };
+
+ /*
+ * This pin is used in the SCFW as a UART. Using it from
+ * Linux would require rewritting the SCFW board file.
+ */
+ pinctrl_hog_scfw: hogscfwgrp {
+ fsl,pins = <
+ IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */
+ >;
+ };
+
+ /* On Module I2C */
+ pinctrl_i2c0: i2c0grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
+ IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
+ >;
+ };
+
+ /* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
+ pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */
+ IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */
+ >;
+ };
+
+ /* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
+ pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */
+ IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */
+ >;
+ };
+
+ /* Colibri I2C */
+ pinctrl_i2c1: i2c1grp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */
+ IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
+ >;
+ };
+
+ /* Colibri Parallel RGB LCD Interface */
+ pinctrl_lcdif: lcdifgrp {
+ fsl,pins = <
+ IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
+ IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
+ IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
+ IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
+ IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
+ IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
+ IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
+ IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
+ IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */
+ IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */
+ IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
+ IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
+ IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
+ IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
+ IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
+ IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
+ IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
+ IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
+ IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
+ IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
+ IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
+ IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
+ IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
+ >;
+ };
+
+ /* Colibri SPI */
+ pinctrl_lpspi2: lpspi2grp {
+ fsl,pins = <
+ IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
+ IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
+ >;
+ };
+
+ /* Colibri UART_B */
+ pinctrl_lpuart0: lpuart0grp {
+ fsl,pins = <
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
+ IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
+ IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
+ >;
+ };
+
+ /* Colibri UART_C */
+ pinctrl_lpuart2: lpuart2grp {
+ fsl,pins = <
+ IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */
+ IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */
+ >;
+ };
+
+ /* Colibri UART_A */
+ pinctrl_lpuart3: lpuart3grp {
+ fsl,pins = <
+ IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */
+ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
+ >;
+ };
+
+ /* Colibri UART_A Control */
+ pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
+ fsl,pins = <
+ IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
+ IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
+ IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
+ IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
+ IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
+ >;
+ };
+
+ /* On module wifi module */
+ pinctrl_pcieb: pciebgrp {
+ fsl,pins = <
+ IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
+ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
+ IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
+ >;
+ };
+
+ /* Colibri PWM_A */
+ pinctrl_pwm_a: pwmagrp {
+ /* both pins are connected together, reserve the unused CSI_D05 */
+ fsl,pins = <
+ IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */
+ IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */
+ >;
+ };
+
+ /* Colibri PWM_B */
+ pinctrl_pwm_b: pwmbgrp {
+ fsl,pins = <
+ IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */
+ >;
+ };
+
+ /* Colibri PWM_C */
+ pinctrl_pwm_c: pwmcgrp {
+ fsl,pins = <
+ IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */
+ >;
+ };
+
+ /* Colibri PWM_D */
+ pinctrl_pwm_d: pwmdgrp {
+ /* both pins are connected together, reserve the unused CSI_D04 */
+ fsl,pins = <
+ IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */
+ IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
+ >;
+ };
+
+ /* On-module I2S */
+ pinctrl_sai0: sai0grp {
+ fsl,pins = <
+ IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
+ IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
+ IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
+ IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
+ >;
+ };
+
+ /* Colibri Audio Analogue Microphone GND */
+ pinctrl_sgtl5000: sgtl5000grp {
+ fsl,pins = <
+ /* MIC GND EN */
+ IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41
+ >;
+ };
+
+ /* On-module SGTL5000 clock */
+ pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
+ fsl,pins = <
+ IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21
+ >;
+ };
+
+ /* On-module USB interrupt */
+ pinctrl_usb3503a: usb3503agrp {
+ fsl,pins = <
+ IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61
+ >;
+ };
+
+ /* Colibri USB Client Cable Detect */
+ pinctrl_usbc_det: usbcdetgrp {
+ fsl,pins = <
+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */
+ >;
+ };
+
+ /* USB Host Power Enable */
+ pinctrl_usbh1_reg: usbh1reggrp {
+ fsl,pins = <
+ IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */
+ >;
+ };
+
+ /* On-module eMMC */
+ pinctrl_usdhc1: usdhc1grp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
+ fsl,pins = <
+ IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
+ IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
+ IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
+ IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
+ IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
+ IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
+ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
+ IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
+ IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
+ IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
+ IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ >;
+ };
+
+ /* Colibri SD/MMC Card Detect */
+ pinctrl_usdhc2_gpio: usdhc2gpiogrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */
+ >;
+ };
+
+ pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
+ fsl,pins = <
+ IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */
+ >;
+ };
+
+ /* Colibri SD/MMC Card */
+ pinctrl_usdhc2: usdhc2grp {
+ fsl,pins = <
+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
+ fsl,pins = <
+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
+ fsl,pins = <
+ IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
+ IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
+ IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
+ IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
+ IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
+ IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_usdhc2_sleep: usdhc2slpgrp {
+ fsl,pins = <
+ IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */
+ IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */
+ IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */
+ IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */
+ IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */
+ IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */
+ IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
+ >;
+ };
+
+ pinctrl_wifi: wifigrp {
+ fsl,pins = <
+ IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
+ >;
+ };
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants
2023-03-08 12:52 ` [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants Philippe Schenker
@ 2023-03-08 14:33 ` Krzysztof Kozlowski
2023-03-08 15:21 ` Philippe Schenker
0 siblings, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 14:33 UTC (permalink / raw)
To: Philippe Schenker, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
On 08/03/2023 13:52, Philippe Schenker wrote:
> From: Philippe Schenker <philippe.schenker@toradex.com>
Subject: Split? Or Rename? Because prepare is too vague.
>
> Toradex sells the Colibri iMX8X module in variants with the i.MX 8QXP
> and i.MX8DX SoC. Prepare for this by moving majority of stuff from
> imx8qxp-colibri.dtsi into imx8x-colibri.dtsi.
>
> Remove DX from the model string.
>
> This commit intends no functional change.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> ---
>
> .../dts/freescale/imx8qxp-colibri-eval-v3.dts | 4 +-
> .../boot/dts/freescale/imx8qxp-colibri.dtsi | 590 +----------------
> ...val-v3.dtsi => imx8x-colibri-eval-v3.dtsi} | 0
> .../boot/dts/freescale/imx8x-colibri.dtsi | 593 ++++++++++++++++++
Use proper -B/-C/-M settings so copy will be detected. It's not possible
to review it otherwise.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants
2023-03-08 14:33 ` Krzysztof Kozlowski
@ 2023-03-08 15:21 ` Philippe Schenker
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 15:21 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
On Wed, 2023-03-08 at 15:33 +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 13:52, Philippe Schenker wrote:
> > From: Philippe Schenker <philippe.schenker@toradex.com>
>
> Subject: Split? Or Rename? Because prepare is too vague.
>
> >
> > Toradex sells the Colibri iMX8X module in variants with the i.MX
> > 8QXP
> > and i.MX8DX SoC. Prepare for this by moving majority of stuff from
> > imx8qxp-colibri.dtsi into imx8x-colibri.dtsi.
> >
> > Remove DX from the model string.
> >
> > This commit intends no functional change.
> >
> > Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> > ---
> >
> > .../dts/freescale/imx8qxp-colibri-eval-v3.dts | 4 +-
> > .../boot/dts/freescale/imx8qxp-colibri.dtsi | 590 +--------------
> > --
> > ...val-v3.dtsi => imx8x-colibri-eval-v3.dtsi} | 0
> > .../boot/dts/freescale/imx8x-colibri.dtsi | 593
> > ++++++++++++++++++
>
> Use proper -B/-C/-M settings so copy will be detected. It's not
> possible
> to review it otherwise.
Thank you! I wasn't aware of these options. They look nice, will try to
make look it better in v2!
>
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v1 02/25] arm64: dts: colibri-imx8x: Update spdx license
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties Philippe Schenker
` (22 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
GPL-2.0+ is deprecated, update it to GPL-2.0-or-later.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts | 2 +-
arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 2 +-
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
index 413a9e9d6c28..fe4597a6f7e0 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-eval-v3.dts
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
index 1ffc42f4a4b3..0f1aa31dd3e5 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index 7c334b93db3b..dc0339b35a3c 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index cb22bde19ea0..12056b77d22e 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -1,4 +1,4 @@
-// SPDX-License-Identifier: GPL-2.0+ OR MIT
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/*
* Copyright 2019 Toradex
*/
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 01/25] arm64: dts: colibri-imx8x: Prepare for qxp and dx variants Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 02/25] arm64: dts: colibri-imx8x: Update spdx license Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:57 ` Krzysztof Kozlowski
2023-03-08 12:52 ` [PATCH v1 04/25] arm64: dts: colibri-imx8x: Use new bracket format Philippe Schenker
` (21 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Sort properties according to the following order and inside these
alphabetically.
1. compatible
2. reg
3. standard properties
4. specific properties
5. status
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../boot/dts/freescale/imx8x-colibri.dtsi | 142 +++++++++---------
1 file changed, 71 insertions(+), 71 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 12056b77d22e..6f86a83bc957 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -10,9 +10,9 @@ chosen {
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
- regulator-name = "+V3.3";
- regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "+V3.3";
};
};
@@ -20,26 +20,26 @@ reg_module_3v3: regulator-module-3v3 {
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
- clock-frequency = <100000>;
- pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>, <&pinctrl_sgtl5000_usb_clk>;
+ pinctrl-names = "default";
+ clock-frequency = <100000>;
status = "okay";
/* Touch controller */
touchscreen@2c {
compatible = "adi,ad7879-1";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ad7879_int>;
reg = <0x2c>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <5 IRQ_TYPE_EDGE_FALLING>;
- touchscreen-max-pressure = <4096>;
- adi,resistance-plate-x = <120>;
- adi,first-conversion-delay = /bits/ 8 <3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_ad7879_int>;
adi,acquisition-time = /bits/ 8 <1>;
- adi,median-filter-size = /bits/ 8 <2>;
adi,averaging = /bits/ 8 <1>;
adi,conversion-interval = /bits/ 8 <255>;
+ adi,first-conversion-delay = /bits/ 8 <3>;
+ adi,median-filter-size = /bits/ 8 <2>;
+ adi,resistance-plate-x = <120>;
+ touchscreen-max-pressure = <4096>;
};
};
@@ -47,9 +47,9 @@ touchscreen@2c {
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
- clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
+ clock-frequency = <100000>;
};
/* Colibri UART_B */
@@ -75,9 +75,9 @@ &fec1 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_fec1>;
pinctrl-1 = <&pinctrl_fec1_sleep>;
- phy-mode = "rmii";
- phy-handle = <ðphy0>;
fsl,magic-packet;
+ phy-handle = <ðphy0>;
+ phy-mode = "rmii";
mdio {
#address-cells = <1>;
@@ -85,36 +85,36 @@ mdio {
ethphy0: ethernet-phy@2 {
compatible = "ethernet-phy-ieee802.3-c22";
- max-speed = <100>;
reg = <2>;
+ max-speed = <100>;
};
};
};
/* On-module eMMC */
&usdhc1 {
- bus-width = <8>;
- non-removable;
- no-sd;
- no-sdio;
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
+ bus-width = <8>;
+ no-sd;
+ no-sdio;
+ non-removable;
status = "okay";
};
/* Colibri SD/MMC Card */
&usdhc2 {
- bus-width = <4>;
- cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
- vmmc-supply = <®_module_3v3>;
pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>;
+ bus-width = <4>;
+ cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
disable-wp;
+ vmmc-supply = <®_module_3v3>;
};
&iomuxc {
@@ -162,14 +162,14 @@ pinctrl_fec1: fec1grp {
fsl,pins = <
IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
+ IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
+ IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
+ IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
+ IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
>;
};
@@ -177,38 +177,38 @@ pinctrl_fec1_sleep: fec1slpgrp {
fsl,pins = <
IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
- IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
- IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
- IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
- IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
+ IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
+ IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
+ IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
+ IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
>;
};
/* Colibri optional CAN on UART_B RTS/CTS */
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
- IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
+ IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
>;
};
/* Colibri optional CAN on PS2 */
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <
- IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
+ IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
>;
};
/* Colibri optional CAN on UART_A TXD/RXD */
pinctrl_flexcan3: flexcan2grp {
fsl,pins = <
- IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
+ IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
>;
};
@@ -227,32 +227,32 @@ IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
pinctrl_hog0: hog0grp {
fsl,pins = <
- IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
- IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
- IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
- IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
+ IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
+ IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
- IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
- IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
- IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
- IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
+ IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
+ IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
+ IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
+ IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
+ IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
+ IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
- IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
- IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
- IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
- IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
- IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
- IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
- IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
- IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
- IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
+ IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
+ IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
+ IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
+ IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
+ IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
+ IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
+ IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
+ IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
+ IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
>;
};
@@ -308,13 +308,8 @@ IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
/* Colibri Parallel RGB LCD Interface */
pinctrl_lcdif: lcdifgrp {
fsl,pins = <
- IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
- IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
- IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
- IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
- IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
+ IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
@@ -324,15 +319,20 @@ IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
+ IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
+ IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
+ IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
+ IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
- IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
+ IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
+ IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
- IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
- IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
- IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
+ IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
+ IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
+ IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
>;
};
@@ -340,19 +340,19 @@ IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
pinctrl_lpspi2: lpspi2grp {
fsl,pins = <
IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
+ IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
+ IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
>;
};
/* Colibri UART_B */
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
+ IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
+ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
>;
};
@@ -375,12 +375,12 @@ IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
/* Colibri UART_A Control */
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
fsl,pins = <
+ IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
+ IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
- IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
- IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
+ IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
- IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
>;
};
@@ -388,8 +388,8 @@ IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
pinctrl_pcieb: pciebgrp {
fsl,pins = <
IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
- IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
+ IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
>;
};
@@ -428,9 +428,9 @@ IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
/* On-module I2S */
pinctrl_sai0: sai0grp {
fsl,pins = <
- IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
+ IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
>;
};
@@ -484,8 +484,8 @@ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
>;
};
@@ -501,8 +501,8 @@ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
>;
};
@@ -518,8 +518,8 @@ IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
+ IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
>;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 12:52 ` [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties Philippe Schenker
@ 2023-03-08 12:57 ` Krzysztof Kozlowski
2023-03-08 13:29 ` Philippe Schenker
2023-03-09 12:19 ` Francesco Dolcini
0 siblings, 2 replies; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 12:57 UTC (permalink / raw)
To: Philippe Schenker, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
On 08/03/2023 13:52, Philippe Schenker wrote:
> From: Philippe Schenker <philippe.schenker@toradex.com>
>
> Sort properties according to the following order and inside these
> alphabetically.
>
> 1. compatible
> 2. reg
> 3. standard properties
> 4. specific properties
> 5. status
Is this approved coding style for IMX DTS?
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> ---
>
> .../boot/dts/freescale/imx8x-colibri.dtsi | 142 +++++++++---------
> 1 file changed, 71 insertions(+), 71 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
> index 12056b77d22e..6f86a83bc957 100644
> --- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
> @@ -10,9 +10,9 @@ chosen {
>
> reg_module_3v3: regulator-module-3v3 {
> compatible = "regulator-fixed";
> - regulator-name = "+V3.3";
> - regulator-min-microvolt = <3300000>;
> regulator-max-microvolt = <3300000>;
> + regulator-min-microvolt = <3300000>;
> +
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 12:57 ` Krzysztof Kozlowski
@ 2023-03-08 13:29 ` Philippe Schenker
2023-03-08 14:32 ` Krzysztof Kozlowski
2023-03-09 12:19 ` Francesco Dolcini
1 sibling, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 13:29 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On Wed, 2023-03-08 at 13:57 +0100, Krzysztof Kozlowski wrote:
> Is this approved coding style for IMX DTS?
How the ordering should be done is nowhere specifically documented (at
least this is my current understanding).
The ordering how I noted it is what we gathered from multiple feedback
on mailinglist discussions.
With that ordering I hope everyone is happy.
Philippe
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 13:29 ` Philippe Schenker
@ 2023-03-08 14:32 ` Krzysztof Kozlowski
2023-03-08 14:50 ` Philippe Schenker
0 siblings, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 14:32 UTC (permalink / raw)
To: dev, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On 08/03/2023 14:29, Philippe Schenker wrote:
> On Wed, 2023-03-08 at 13:57 +0100, Krzysztof Kozlowski wrote:
>> Is this approved coding style for IMX DTS?
>
> How the ordering should be done is nowhere specifically documented (at
> least this is my current understanding).
> The ordering how I noted it is what we gathered from multiple feedback
> on mailinglist discussions.
>
> With that ordering I hope everyone is happy.
>
> Philippe
Yeah, but what if next developer next month re-orders all your nodes
again because he will use different coding style?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 14:32 ` Krzysztof Kozlowski
@ 2023-03-08 14:50 ` Philippe Schenker
2023-03-08 16:09 ` Krzysztof Kozlowski
0 siblings, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 14:50 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On Wed, 2023-03-08 at 15:32 +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 14:29, Philippe Schenker wrote:
> > On Wed, 2023-03-08 at 13:57 +0100, Krzysztof Kozlowski wrote:
> > > Is this approved coding style for IMX DTS?
> >
> > How the ordering should be done is nowhere specifically documented
> > (at
> > least this is my current understanding).
> > The ordering how I noted it is what we gathered from multiple
> > feedback
> > on mailinglist discussions.
> >
> > With that ordering I hope everyone is happy.
> >
> > Philippe
>
> Yeah, but what if next developer next month re-orders all your nodes
> again because he will use different coding style?
Someone from Toradex will complain that we want to have it the way I
sent now, since this is the way we agreed on internally.
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 14:50 ` Philippe Schenker
@ 2023-03-08 16:09 ` Krzysztof Kozlowski
0 siblings, 0 replies; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 16:09 UTC (permalink / raw)
To: dev, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On 08/03/2023 15:50, Philippe Schenker wrote:
> On Wed, 2023-03-08 at 15:32 +0100, Krzysztof Kozlowski wrote:
>> On 08/03/2023 14:29, Philippe Schenker wrote:
>>> On Wed, 2023-03-08 at 13:57 +0100, Krzysztof Kozlowski wrote:
>>>> Is this approved coding style for IMX DTS?
>>>
>>> How the ordering should be done is nowhere specifically documented
>>> (at
>>> least this is my current understanding).
>>> The ordering how I noted it is what we gathered from multiple
>>> feedback
>>> on mailinglist discussions.
>>>
>>> With that ordering I hope everyone is happy.
>>>
>>> Philippe
>>
>> Yeah, but what if next developer next month re-orders all your nodes
>> again because he will use different coding style?
>
> Someone from Toradex will complain that we want to have it the way I
> sent now, since this is the way we agreed on internally.
I am sorry, but coding style is per subsystem, not per Toradex boards.
Even if my example is not applicable, someone might come soon with
something different for entire iMX and again re-order it.
Either make a rule for entire iMX or do not make re-shufflings. They are
not useful.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-08 12:57 ` Krzysztof Kozlowski
2023-03-08 13:29 ` Philippe Schenker
@ 2023-03-09 12:19 ` Francesco Dolcini
2023-03-14 8:17 ` Shawn Guo
1 sibling, 1 reply; 42+ messages in thread
From: Francesco Dolcini @ 2023-03-09 12:19 UTC (permalink / raw)
To: Krzysztof Kozlowski, Shawn Guo
Cc: Philippe Schenker, devicetree, Sascha Hauer, NXP Linux Team,
Krzysztof Kozlowski, Rob Herring, Pengutronix Kernel Team,
Frank Rowand, linux-arm-kernel, Fabio Estevam, Philippe Schenker,
linux-kernel, Marcel Ziswiler
Hello Krzysztof, first thanks for your review.
Let's try to get some clarity on this with the help of Shawn.
On Wed, Mar 08, 2023 at 01:57:38PM +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 13:52, Philippe Schenker wrote:
> > From: Philippe Schenker <philippe.schenker@toradex.com>
> >
> > Sort properties according to the following order and inside these
> > alphabetically.
> >
> > 1. compatible
> > 2. reg
> > 3. standard properties
> > 4. specific properties
> > 5. status
>
> Is this approved coding style for IMX DTS?
I 100% understand your concerns here.
With that said let me try to briefly explain the reasoning here, in
various threads we were asked in the past to move node around based on
some not 100% defined rules [0][1].
On Sun, 2023-01-29 at 11:19 +0800, Shawn Guo wrote:
>> +&usbotg1 {
>> + adp-disable;
>> + ci-disable-lpm;
>> + hnp-disable;
>> + over-current-active-low;
>> + pinctrl-names = "default";
>> + pinctrl-0 = <&pinctrl_usbotg1>;
>
>We generally want to put such generic properties before device specific
>ones.
In addition to that we find convenient to have properties sorted
alphabetically when no other rule is available, it just prevents any
kind of discussion, minimize merge conflicts and make comparing files
easier.
I also agree that the difference between "generic"/"specific" is fuzzy
at best.
With all that said ...
Shawn: What should we do? We can of course avoid any kind of re-ordering
from now on.
I am fine to be very pragmatic here, no-reordering on existing DTS
files, newly added DTS files we discuss whatever is the reasoning of the
reviewer/maintainer on a case-by-case basis.
Francesco
[0] https://lore.kernel.org/all/895e7df5-65e5-7b26-81d6-864e68957ab6@linaro.org/
[1] https://lore.kernel.org/all/20230129031932.GO20713@T480/
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-09 12:19 ` Francesco Dolcini
@ 2023-03-14 8:17 ` Shawn Guo
2023-03-14 8:25 ` Francesco Dolcini
0 siblings, 1 reply; 42+ messages in thread
From: Shawn Guo @ 2023-03-14 8:17 UTC (permalink / raw)
To: Francesco Dolcini
Cc: Krzysztof Kozlowski, Philippe Schenker, devicetree, Sascha Hauer,
NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel, Marcel Ziswiler
On Thu, Mar 09, 2023 at 01:19:13PM +0100, Francesco Dolcini wrote:
> Hello Krzysztof, first thanks for your review.
>
> Let's try to get some clarity on this with the help of Shawn.
>
> On Wed, Mar 08, 2023 at 01:57:38PM +0100, Krzysztof Kozlowski wrote:
> > On 08/03/2023 13:52, Philippe Schenker wrote:
> > > From: Philippe Schenker <philippe.schenker@toradex.com>
> > >
> > > Sort properties according to the following order and inside these
> > > alphabetically.
> > >
> > > 1. compatible
> > > 2. reg
> > > 3. standard properties
> > > 4. specific properties
> > > 5. status
> >
> > Is this approved coding style for IMX DTS?
>
> I 100% understand your concerns here.
>
> With that said let me try to briefly explain the reasoning here, in
> various threads we were asked in the past to move node around based on
> some not 100% defined rules [0][1].
>
> On Sun, 2023-01-29 at 11:19 +0800, Shawn Guo wrote:
> >> +&usbotg1 {
> >> + adp-disable;
> >> + ci-disable-lpm;
> >> + hnp-disable;
> >> + over-current-active-low;
> >> + pinctrl-names = "default";
> >> + pinctrl-0 = <&pinctrl_usbotg1>;
> >
> >We generally want to put such generic properties before device specific
> >ones.
>
> In addition to that we find convenient to have properties sorted
> alphabetically when no other rule is available, it just prevents any
> kind of discussion, minimize merge conflicts and make comparing files
> easier.
>
> I also agree that the difference between "generic"/"specific" is fuzzy
> at best.
>
> With all that said ...
>
> Shawn: What should we do? We can of course avoid any kind of re-ordering
> from now on.
We are practically asking for 1, 2 and 5 for i.MX DTS files, but pretty
flexible for the rest.
> I am fine to be very pragmatic here, no-reordering on existing DTS
> files, newly added DTS files we discuss whatever is the reasoning of the
> reviewer/maintainer on a case-by-case basis.
Sounds good to me! While I personally like your ordering, I do not want
it to churn the existing DTS files.
I'm happy to take this patch as a special case though :)
Shawn
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties
2023-03-14 8:17 ` Shawn Guo
@ 2023-03-14 8:25 ` Francesco Dolcini
0 siblings, 0 replies; 42+ messages in thread
From: Francesco Dolcini @ 2023-03-14 8:25 UTC (permalink / raw)
To: Shawn Guo
Cc: Francesco Dolcini, Krzysztof Kozlowski, Philippe Schenker,
devicetree, Sascha Hauer, NXP Linux Team, Krzysztof Kozlowski,
Rob Herring, Pengutronix Kernel Team, Frank Rowand,
linux-arm-kernel, Fabio Estevam, Philippe Schenker, linux-kernel,
Marcel Ziswiler
On Tue, Mar 14, 2023 at 04:17:35PM +0800, Shawn Guo wrote:
> On Thu, Mar 09, 2023 at 01:19:13PM +0100, Francesco Dolcini wrote:
> > Hello Krzysztof, first thanks for your review.
> >
> > Let's try to get some clarity on this with the help of Shawn.
> >
> > On Wed, Mar 08, 2023 at 01:57:38PM +0100, Krzysztof Kozlowski wrote:
> > > On 08/03/2023 13:52, Philippe Schenker wrote:
> > > > From: Philippe Schenker <philippe.schenker@toradex.com>
> > > >
> > > > Sort properties according to the following order and inside these
> > > > alphabetically.
> > > >
> > > > 1. compatible
> > > > 2. reg
> > > > 3. standard properties
> > > > 4. specific properties
> > > > 5. status
> > >
> > > Is this approved coding style for IMX DTS?
> >
> > I 100% understand your concerns here.
> >
> > With that said let me try to briefly explain the reasoning here, in
> > various threads we were asked in the past to move node around based on
> > some not 100% defined rules [0][1].
> >
> > On Sun, 2023-01-29 at 11:19 +0800, Shawn Guo wrote:
> > >> +&usbotg1 {
> > >> + adp-disable;
> > >> + ci-disable-lpm;
> > >> + hnp-disable;
> > >> + over-current-active-low;
> > >> + pinctrl-names = "default";
> > >> + pinctrl-0 = <&pinctrl_usbotg1>;
> > >
> > >We generally want to put such generic properties before device specific
> > >ones.
> >
> > In addition to that we find convenient to have properties sorted
> > alphabetically when no other rule is available, it just prevents any
> > kind of discussion, minimize merge conflicts and make comparing files
> > easier.
> >
> > I also agree that the difference between "generic"/"specific" is fuzzy
> > at best.
> >
> > With all that said ...
> >
> > Shawn: What should we do? We can of course avoid any kind of re-ordering
> > from now on.
>
> We are practically asking for 1, 2 and 5 for i.MX DTS files, but pretty
> flexible for the rest.
>
> > I am fine to be very pragmatic here, no-reordering on existing DTS
> > files, newly added DTS files we discuss whatever is the reasoning of the
> > reviewer/maintainer on a case-by-case basis.
>
> Sounds good to me! While I personally like your ordering, I do not want
> it to churn the existing DTS files.
Agreed.
>
> I'm happy to take this patch as a special case though :)
Philippe just rebased all the stuff getting rid of the sort commit :-)
No special case needed, he will send an updated series in a hour.
Thanks a lot,
Francesco
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v1 04/25] arm64: dts: colibri-imx8x: Use new bracket format
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (2 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 03/25] arm64: dts: colibri-imx8x: Sort properties Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 05/25] arm64: dts: colibri-imx8x: Add atmel pinctrl groups Philippe Schenker
` (20 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Use the new bracket format as described by Rob since this seems the
format that we're heading in the future.
https://lore.kernel.org/all/CAL_JsqKqQdRZC08-BGJqTjzJZ8aWA41LHMbv0QyyVePVm0co7A@mail.gmail.com/
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../boot/dts/freescale/imx8x-colibri.dtsi | 497 +++++++-----------
1 file changed, 202 insertions(+), 295 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 6f86a83bc957..7fea99206020 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -123,144 +123,116 @@ &iomuxc {
/* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21
- >;
+ fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SCL_LSIO_GPIO3_IO05 0x21>;
};
/* Colibri Analogue Inputs */
pinctrl_adc0: adc0grp {
- fsl,pins = <
- IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60 /* SODIMM 8 */
- IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60 /* SODIMM 6 */
- IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60 /* SODIMM 4 */
- IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60 /* SODIMM 2 */
- >;
+ fsl,pins = <IMX8QXP_ADC_IN0_ADMA_ADC_IN0 0x60>, /* SODIMM 8 */
+ <IMX8QXP_ADC_IN1_ADMA_ADC_IN1 0x60>, /* SODIMM 6 */
+ <IMX8QXP_ADC_IN4_ADMA_ADC_IN4 0x60>, /* SODIMM 4 */
+ <IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */
};
pinctrl_can_int: canintgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40 /* SODIMM 73 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */
};
pinctrl_csi_ctl: csictlgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20 /* SODIMM 77 */
- IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20 /* SODIMM 89 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>, /* SODIMM 77 */
+ <IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */
};
pinctrl_ext_io0: extio0grp {
- fsl,pins = <
- IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040 /* SODIMM 135 */
- >;
+ fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */
};
/* Colibri Ethernet: On-module 100Mbps PHY Micrel KSZ8041 */
pinctrl_fec1: fec1grp {
- fsl,pins = <
- IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020
- IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
- IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61
- IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61
- IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61
- IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61
- IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61
- IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061
- IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61
- IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61
- >;
+ fsl,pins = <IMX8QXP_ENET0_MDC_CONN_ENET0_MDC 0x06000020>,
+ <IMX8QXP_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020>,
+ <IMX8QXP_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x61>,
+ <IMX8QXP_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x61>,
+ <IMX8QXP_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x61>,
+ <IMX8QXP_ENET0_RGMII_RXD2_CONN_ENET0_RMII_RX_ER 0x61>,
+ <IMX8QXP_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x61>,
+ <IMX8QXP_ENET0_RGMII_TXC_CONN_ENET0_RCLK50M_OUT 0x06000061>,
+ <IMX8QXP_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x61>,
+ <IMX8QXP_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x61>;
};
pinctrl_fec1_sleep: fec1slpgrp {
- fsl,pins = <
- IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041
- IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041
- IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41
- IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41
- IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41
- IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41
- IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41
- IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41
- IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41
- IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41
- >;
+ fsl,pins = <IMX8QXP_ENET0_MDC_LSIO_GPIO5_IO11 0x06000041>,
+ <IMX8QXP_ENET0_MDIO_LSIO_GPIO5_IO10 0x06000041>,
+ <IMX8QXP_ENET0_RGMII_RX_CTL_LSIO_GPIO5_IO04 0x41>,
+ <IMX8QXP_ENET0_RGMII_RXD0_LSIO_GPIO5_IO05 0x41>,
+ <IMX8QXP_ENET0_RGMII_RXD1_LSIO_GPIO5_IO06 0x41>,
+ <IMX8QXP_ENET0_RGMII_RXD2_LSIO_GPIO5_IO07 0x41>,
+ <IMX8QXP_ENET0_RGMII_TX_CTL_LSIO_GPIO4_IO30 0x41>,
+ <IMX8QXP_ENET0_RGMII_TXC_LSIO_GPIO4_IO29 0x41>,
+ <IMX8QXP_ENET0_RGMII_TXD0_LSIO_GPIO4_IO31 0x41>,
+ <IMX8QXP_ENET0_RGMII_TXD1_LSIO_GPIO5_IO00 0x41>;
};
/* Colibri optional CAN on UART_B RTS/CTS */
pinctrl_flexcan1: flexcan0grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 /* SODIMM 34 */
- IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 /* SODIMM 32 */
- >;
+ fsl,pins = <IMX8QXP_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21>, /* SODIMM 34 */
+ <IMX8QXP_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21>; /* SODIMM 32 */
};
/* Colibri optional CAN on PS2 */
pinctrl_flexcan2: flexcan1grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 /* SODIMM 63 */
- IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 /* SODIMM 55 */
- >;
+ fsl,pins = <IMX8QXP_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21>, /* SODIMM 63 */
+ <IMX8QXP_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21>; /* SODIMM 55 */
};
/* Colibri optional CAN on UART_A TXD/RXD */
pinctrl_flexcan3: flexcan2grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21 /* SODIMM 33 */
- IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21 /* SODIMM 35 */
- >;
+ fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_FLEXCAN2_RX 0x21>, /* SODIMM 33 */
+ <IMX8QXP_FLEXCAN2_TX_ADMA_FLEXCAN2_TX 0x21>; /* SODIMM 35 */
};
/* Colibri LCD Back-Light GPIO */
pinctrl_gpio_bl_on: gpioblongrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60 /* SODIMM 71 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */
};
pinctrl_gpiokeys: gpiokeysgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041 /* SODIMM 45 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
};
pinctrl_hog0: hog0grp {
- fsl,pins = <
- IMX8QXP_CSI_D00_CI_PI_D02 0x61 /* SODIMM 101 */
- IMX8QXP_CSI_D01_CI_PI_D03 0x61 /* SODIMM 103 */
- IMX8QXP_CSI_D02_CI_PI_D04 0x61 /* SODIMM 79 */
- IMX8QXP_CSI_D03_CI_PI_D05 0x61 /* SODIMM 97 */
- IMX8QXP_CSI_D06_CI_PI_D08 0x61 /* SODIMM 85 */
- IMX8QXP_CSI_D07_CI_PI_D09 0x61 /* SODIMM 65 */
- IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20 /* SODIMM 96 */
- IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020 /* SODIMM 85 */
- IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020 /* SODIMM 65 */
- IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20 /* SODIMM 69 */
- IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20 /* SODIMM 99 */
- IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20 /* SODIMM 105 */
- IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20 /* SODIMM 107 */
- IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20 /* SODIMM 98 */
- IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20 /* SODIMM 102 */
- IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20 /* SODIMM 95 */
- IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20 /* SODIMM 104 */
- IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20 /* SODIMM 106 */
- IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20 /* SODIMM 97 */
- IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20 /* SODIMM 79 */
- IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20 /* SODIMM 103 */
- IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20 /* SODIMM 101 */
- IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20 /* SODIMM 100 */
- IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20 /* SODIMM 133 */
- IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20 /* SODIMM 127 */
- IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20 /* SODIMM 131 */
- >;
+ fsl,pins = <IMX8QXP_CSI_D00_CI_PI_D02 0x61>, /* SODIMM 101 */
+ <IMX8QXP_CSI_D01_CI_PI_D03 0x61>, /* SODIMM 103 */
+ <IMX8QXP_CSI_D02_CI_PI_D04 0x61>, /* SODIMM 79 */
+ <IMX8QXP_CSI_D03_CI_PI_D05 0x61>, /* SODIMM 97 */
+ <IMX8QXP_CSI_D06_CI_PI_D08 0x61>, /* SODIMM 85 */
+ <IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */
+ <IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */
+ <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
+ <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020>, /* SODIMM 65 */
+ <IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
+ <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
+ <IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
+ <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20>, /* SODIMM 107 */
+ <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
+ <IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */
+ <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
+ <IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>, /* SODIMM 104 */
+ <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20>, /* SODIMM 106 */
+ <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
+ <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
+ <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
+ <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
+ <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>, /* SODIMM 100 */
+ <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
+ <IMX8QXP_USB_SS3_TC2_LSIO_GPIO4_IO05 0x20>, /* SODIMM 127 */
+ <IMX8QXP_USB_SS3_TC3_LSIO_GPIO4_IO06 0x20>; /* SODIMM 131 */
};
pinctrl_hog1: hog1grp {
- fsl,pins = <
- IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20 /* SODIMM 75 */
- IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
- >;
+ fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>, /* SODIMM 75 */
+ <IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
};
/*
@@ -268,326 +240,261 @@ IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20 /* SODIMM 93 */
* Linux would require rewritting the SCFW board file.
*/
pinctrl_hog_scfw: hogscfwgrp {
- fsl,pins = <
- IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20 /* SODIMM 144 */
- >;
+ fsl,pins = <IMX8QXP_SCU_GPIO0_00_LSIO_GPIO2_IO03 0x20>; /* SODIMM 144 */
};
/* On Module I2C */
pinctrl_i2c0: i2c0grp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021
- IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021
- >;
+ fsl,pins = <IMX8QXP_MIPI_CSI0_GPIO0_00_ADMA_I2C0_SCL 0x06000021>,
+ <IMX8QXP_MIPI_CSI0_GPIO0_01_ADMA_I2C0_SDA 0x06000021>;
};
/* MIPI DSI I2C accessible on SODIMM (X1) and FFC (X2) */
pinctrl_i2c0_mipi_lvds0: i2c0mipilvds0grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 /* SODIMM 140 */
- IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 /* SODIMM 142 */
- >;
+ fsl,pins = <IMX8QXP_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020>, /* SODIMM 140 */
+ <IMX8QXP_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020>; /* SODIMM 142 */
};
/* MIPI CSI I2C accessible on SODIMM (X1) and FFC (X3) */
pinctrl_i2c0_mipi_lvds1: i2c0mipilvds1grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 /* SODIMM 186 */
- IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 /* SODIMM 188 */
- >;
+ fsl,pins = <IMX8QXP_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020>, /* SODIMM 186 */
+ <IMX8QXP_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020>; /* SODIMM 188 */
};
/* Colibri I2C */
pinctrl_i2c1: i2c1grp {
- fsl,pins = <
- IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021 /* SODIMM 196 */
- IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021 /* SODIMM 194 */
- >;
+ fsl,pins = <IMX8QXP_MIPI_DSI0_GPIO0_00_ADMA_I2C1_SCL 0x06000021>, /* SODIMM 196 */
+ <IMX8QXP_MIPI_DSI0_GPIO0_01_ADMA_I2C1_SDA 0x06000021>; /* SODIMM 194 */
};
/* Colibri Parallel RGB LCD Interface */
pinctrl_lcdif: lcdifgrp {
- fsl,pins = <
- IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60 /* SODIMM 57 */
- IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60 /* SODIMM 76 */
- IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60 /* SODIMM 70 */
- IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60 /* SODIMM 60 */
- IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60 /* SODIMM 58 */
- IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60 /* SODIMM 78 */
- IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60 /* SODIMM 72 */
- IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60 /* SODIMM 80 */
- IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60 /* SODIMM 46 */
- IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60 /* SODIMM 62 */
- IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60 /* SODIMM 48 */
- IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60 /* SODIMM 82 */
- IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60 /* SODIMM 44 */
- IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60 /* SODIMM 56 */
- IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60 /* SODIMM 52 */
- IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60 /* SODIMM 74 */
- IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60 /* SODIMM 50 */
- IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60 /* SODIMM 68 */
- IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60 /* SODIMM 57 */
- IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60 /* SODIMM 54 */
- IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60 /* SODIMM 64 */
- IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60 /* SODIMM 66 */
- IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60 /* SODIMM 61 */
- IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60 /* SODIMM 44 */
- IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60 /* SODIMM 76 */
- >;
+ fsl,pins = <IMX8QXP_ENET0_RGMII_TXD2_LSIO_GPIO5_IO01 0x60>, /* SODIMM 57 */
+ <IMX8QXP_ESAI0_FSR_ADMA_LCDIF_D00 0x60>, /* SODIMM 76 */
+ <IMX8QXP_ESAI0_FST_ADMA_LCDIF_D01 0x60>, /* SODIMM 70 */
+ <IMX8QXP_ESAI0_SCKR_ADMA_LCDIF_D02 0x60>, /* SODIMM 60 */
+ <IMX8QXP_ESAI0_SCKT_ADMA_LCDIF_D03 0x60>, /* SODIMM 58 */
+ <IMX8QXP_ESAI0_TX0_ADMA_LCDIF_D04 0x60>, /* SODIMM 78 */
+ <IMX8QXP_ESAI0_TX1_ADMA_LCDIF_D05 0x60>, /* SODIMM 72 */
+ <IMX8QXP_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x60>, /* SODIMM 80 */
+ <IMX8QXP_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x60>, /* SODIMM 46 */
+ <IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */
+ <IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */
+ <IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */
+ <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60>, /* SODIMM 44 */
+ <IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */
+ <IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */
+ <IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */
+ <IMX8QXP_SPDIF0_TX_ADMA_LCDIF_D11 0x60>, /* SODIMM 50 */
+ <IMX8QXP_SPI3_CS0_ADMA_LCDIF_HSYNC 0x60>, /* SODIMM 68 */
+ <IMX8QXP_SPI3_CS1_ADMA_LCDIF_D16 0x60>, /* SODIMM 57 */
+ <IMX8QXP_SPI3_SCK_ADMA_LCDIF_D13 0x60>, /* SODIMM 54 */
+ <IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */
+ <IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */
+ <IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>, /* SODIMM 61 */
+ <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60>, /* SODIMM 44 */
+ <IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>; /* SODIMM 76 */
};
/* Colibri SPI */
pinctrl_lpspi2: lpspi2grp {
- fsl,pins = <
- IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21 /* SODIMM 86 */
- IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040 /* SODIMM 88 */
- IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040 /* SODIMM 90 */
- IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040 /* SODIMM 92 */
- >;
+ fsl,pins = <IMX8QXP_SPI2_CS0_LSIO_GPIO1_IO00 0x21>, /* SODIMM 86 */
+ <IMX8QXP_SPI2_SCK_ADMA_SPI2_SCK 0x06000040>, /* SODIMM 88 */
+ <IMX8QXP_SPI2_SDI_ADMA_SPI2_SDI 0x06000040>, /* SODIMM 90 */
+ <IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>; /* SODIMM 92 */
};
/* Colibri UART_B */
pinctrl_lpuart0: lpuart0grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020 /* SODIMM 34 */
- IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020 /* SODIMM 32 */
- IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020 /* SODIMM 36 */
- IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020 /* SODIMM 38 */
- >;
+ fsl,pins = <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */
+ <IMX8QXP_FLEXCAN0_TX_ADMA_UART0_CTS_B 0x06000020>, /* SODIMM 32 */
+ <IMX8QXP_UART0_RX_ADMA_UART0_RX 0x06000020>, /* SODIMM 36 */
+ <IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020>; /* SODIMM 38 */
};
/* Colibri UART_C */
pinctrl_lpuart2: lpuart2grp {
- fsl,pins = <
- IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 /* SODIMM 19 */
- IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 /* SODIMM 21 */
- >;
+ fsl,pins = <IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020>, /* SODIMM 19 */
+ <IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020>; /* SODIMM 21 */
};
/* Colibri UART_A */
pinctrl_lpuart3: lpuart3grp {
- fsl,pins = <
- IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 /* SODIMM 33 */
- IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 /* SODIMM 35 */
- >;
+ fsl,pins = <IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020>, /* SODIMM 33 */
+ <IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020>; /* SODIMM 35 */
};
/* Colibri UART_A Control */
pinctrl_lpuart3_ctrl: lpuart3ctrlgrp {
- fsl,pins = <
- IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20 /* SODIMM 37 */
- IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20 /* SODIMM 29 */
- IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20 /* SODIMM 23 */
- IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20 /* SODIMM 27 */
- IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20 /* SODIMM 25 */
- IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20 /* SODIMM 31 */
- >;
+ fsl,pins = <IMX8QXP_CSI_EN_LSIO_GPIO3_IO02 0x20>, /* SODIMM 37 */
+ <IMX8QXP_CSI_RESET_LSIO_GPIO3_IO03 0x20>, /* SODIMM 29 */
+ <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>, /* SODIMM 23 */
+ <IMX8QXP_SAI1_RXC_LSIO_GPIO0_IO30 0x20>, /* SODIMM 27 */
+ <IMX8QXP_SAI1_RXD_LSIO_GPIO0_IO29 0x20>, /* SODIMM 25 */
+ <IMX8QXP_USDHC1_CD_B_LSIO_GPIO4_IO22 0x20>; /* SODIMM 31 */
};
/* On module wifi module */
pinctrl_pcieb: pciebgrp {
- fsl,pins = <
- IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061 /* SODIMM 178 */
- IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60 /* SODIMM 81 */
- IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061 /* SODIMM 94 */
- >;
+ fsl,pins = <IMX8QXP_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x04000061>, /* SODIMM 178 */
+ <IMX8QXP_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x60>, /* SODIMM 81 */
+ <IMX8QXP_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000061>; /* SODIMM 94 */
};
/* Colibri PWM_A */
pinctrl_pwm_a: pwmagrp {
/* both pins are connected together, reserve the unused CSI_D05 */
- fsl,pins = <
- IMX8QXP_CSI_D05_CI_PI_D07 0x61 /* SODIMM 59 */
- IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60 /* SODIMM 59 */
- >;
+ fsl,pins = <IMX8QXP_CSI_D05_CI_PI_D07 0x61>, /* SODIMM 59 */
+ <IMX8QXP_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x60>; /* SODIMM 59 */
};
/* Colibri PWM_B */
pinctrl_pwm_b: pwmbgrp {
- fsl,pins = <
- IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60 /* SODIMM 28 */
- >;
+ fsl,pins = <IMX8QXP_UART1_TX_LSIO_PWM0_OUT 0x60>; /* SODIMM 28 */
};
/* Colibri PWM_C */
pinctrl_pwm_c: pwmcgrp {
- fsl,pins = <
- IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60 /* SODIMM 30 */
- >;
+ fsl,pins = <IMX8QXP_UART1_RX_LSIO_PWM1_OUT 0x60>; /* SODIMM 30 */
};
/* Colibri PWM_D */
pinctrl_pwm_d: pwmdgrp {
/* both pins are connected together, reserve the unused CSI_D04 */
- fsl,pins = <
- IMX8QXP_CSI_D04_CI_PI_D06 0x61 /* SODIMM 67 */
- IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60 /* SODIMM 67 */
- >;
+ fsl,pins = <IMX8QXP_CSI_D04_CI_PI_D06 0x61>, /* SODIMM 67 */
+ <IMX8QXP_UART1_RTS_B_LSIO_PWM2_OUT 0x60>; /* SODIMM 67 */
};
/* On-module I2S */
pinctrl_sai0: sai0grp {
- fsl,pins = <
- IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040
- IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040
- IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040
- IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040
- >;
+ fsl,pins = <IMX8QXP_SPI0_CS0_ADMA_SAI0_RXD 0x06000040>,
+ <IMX8QXP_SPI0_SCK_ADMA_SAI0_TXC 0x06000040>,
+ <IMX8QXP_SPI0_SDI_ADMA_SAI0_TXD 0x06000040>,
+ <IMX8QXP_SPI0_SDO_ADMA_SAI0_TXFS 0x06000040>;
};
/* Colibri Audio Analogue Microphone GND */
pinctrl_sgtl5000: sgtl5000grp {
- fsl,pins = <
- /* MIC GND EN */
- IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41
- >;
+ fsl,pins = <IMX8QXP_MIPI_CSI0_I2C0_SDA_LSIO_GPIO3_IO06 0x41>;
};
/* On-module SGTL5000 clock */
pinctrl_sgtl5000_usb_clk: sgtl5000usbclkgrp {
- fsl,pins = <
- IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21
- >;
+ fsl,pins = <IMX8QXP_ADC_IN3_ADMA_ACM_MCLK_OUT0 0x21>;
};
/* On-module USB interrupt */
pinctrl_usb3503a: usb3503agrp {
- fsl,pins = <
- IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61
- >;
+ fsl,pins = <IMX8QXP_MIPI_CSI0_MCLK_OUT_LSIO_GPIO3_IO04 0x61>;
};
/* Colibri USB Client Cable Detect */
pinctrl_usbc_det: usbcdetgrp {
- fsl,pins = <
- IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040 /* SODIMM 137 */
- >;
+ fsl,pins = <IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x06000040>; /* SODIMM 137 */
};
/* USB Host Power Enable */
pinctrl_usbh1_reg: usbh1reggrp {
- fsl,pins = <
- IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040 /* SODIMM 129 */
- >;
+ fsl,pins = <IMX8QXP_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000040>; /* SODIMM 129 */
};
/* On-module eMMC */
pinctrl_usdhc1: usdhc1grp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- >;
+ fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
+ <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
+ <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
+ <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
+ <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
+ <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
+ <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
+ <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
+ <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
+ <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
+ <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>,
+ <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>;
};
pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- >;
+ fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
+ <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
+ <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
+ <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
+ <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
+ <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
+ <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
+ <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
+ <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
+ <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
+ <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>,
+ <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>;
};
pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
- fsl,pins = <
- IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
- IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21
- IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21
- IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21
- IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21
- IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21
- IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21
- IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21
- IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21
- IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21
- IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21
- IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41
- >;
+ fsl,pins = <IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041>,
+ <IMX8QXP_EMMC0_CMD_CONN_EMMC0_CMD 0x21>,
+ <IMX8QXP_EMMC0_DATA0_CONN_EMMC0_DATA0 0x21>,
+ <IMX8QXP_EMMC0_DATA1_CONN_EMMC0_DATA1 0x21>,
+ <IMX8QXP_EMMC0_DATA2_CONN_EMMC0_DATA2 0x21>,
+ <IMX8QXP_EMMC0_DATA3_CONN_EMMC0_DATA3 0x21>,
+ <IMX8QXP_EMMC0_DATA4_CONN_EMMC0_DATA4 0x21>,
+ <IMX8QXP_EMMC0_DATA5_CONN_EMMC0_DATA5 0x21>,
+ <IMX8QXP_EMMC0_DATA6_CONN_EMMC0_DATA6 0x21>,
+ <IMX8QXP_EMMC0_DATA7_CONN_EMMC0_DATA7 0x21>,
+ <IMX8QXP_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x21>,
+ <IMX8QXP_EMMC0_STROBE_CONN_EMMC0_STROBE 0x41>;
};
/* Colibri SD/MMC Card Detect */
pinctrl_usdhc2_gpio: usdhc2gpiogrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021 /* SODIMM 43 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x06000021>; /* SODIMM 43 */
};
pinctrl_usdhc2_gpio_sleep: usdhc2gpioslpgrp {
- fsl,pins = <
- IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60 /* SODIMM 43 */
- >;
+ fsl,pins = <IMX8QXP_QSPI0A_DATA0_LSIO_GPIO3_IO09 0x60>; /* SODIMM 43 */
};
/* Colibri SD/MMC Card */
pinctrl_usdhc2: usdhc2grp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
+ fsl,pins = <IMX8QXP_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041>, /* SODIMM 47 */
+ <IMX8QXP_USDHC1_CMD_CONN_USDHC1_CMD 0x21>, /* SODIMM 190 */
+ <IMX8QXP_USDHC1_DATA0_CONN_USDHC1_DATA0 0x21>, /* SODIMM 192 */
+ <IMX8QXP_USDHC1_DATA1_CONN_USDHC1_DATA1 0x21>, /* SODIMM 49 */
+ <IMX8QXP_USDHC1_DATA2_CONN_USDHC1_DATA2 0x21>, /* SODIMM 51 */
+ <IMX8QXP_USDHC1_DATA3_CONN_USDHC1_DATA3 0x21>, /* SODIMM 53 */
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_usdhc2_sleep: usdhc2slpgrp {
- fsl,pins = <
- IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60 /* SODIMM 47 */
- IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60 /* SODIMM 190 */
- IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60 /* SODIMM 192 */
- IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60 /* SODIMM 49 */
- IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60 /* SODIMM 51 */
- IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60 /* SODIMM 53 */
- IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21
- >;
+ fsl,pins = <IMX8QXP_USDHC1_CLK_LSIO_GPIO4_IO23 0x60>, /* SODIMM 47 */
+ <IMX8QXP_USDHC1_CMD_LSIO_GPIO4_IO24 0x60>, /* SODIMM 190 */
+ <IMX8QXP_USDHC1_DATA0_LSIO_GPIO4_IO25 0x60>, /* SODIMM 192 */
+ <IMX8QXP_USDHC1_DATA1_LSIO_GPIO4_IO26 0x60>, /* SODIMM 49 */
+ <IMX8QXP_USDHC1_DATA2_LSIO_GPIO4_IO27 0x60>, /* SODIMM 51 */
+ <IMX8QXP_USDHC1_DATA3_LSIO_GPIO4_IO28 0x60>, /* SODIMM 53 */
+ <IMX8QXP_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x21>;
};
pinctrl_wifi: wifigrp {
- fsl,pins = <
- IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20
- >;
+ fsl,pins = <IMX8QXP_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20>;
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 05/25] arm64: dts: colibri-imx8x: Add atmel pinctrl groups
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (3 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 04/25] arm64: dts: colibri-imx8x: Use new bracket format Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 06/25] arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk Philippe Schenker
` (19 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add pinctrl groups for enabling atmel touchscreen support.
Remove the pads out of pinctrl_hog0 as they now can be enabled more
specific using pinctrl_atmel_conn label.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../boot/dts/freescale/imx8x-colibri.dtsi | 18 ++++++++++++++++--
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 7fea99206020..0b84b65c846a 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -134,6 +134,22 @@ pinctrl_adc0: adc0grp {
<IMX8QXP_ADC_IN5_ADMA_ADC_IN5 0x60>; /* SODIMM 2 */
};
+ /* Atmel MXT touchsceen + Capacitive Touch Adapter */
+ /* NOTE: This pingroup conflicts with pingroups
+ * pinctrl_pwm_b/pinctrl_pwm_c. Don't enable them
+ * simultaneously.
+ */
+ pinctrl_atmel_adap: atmeladaptergrp {
+ fsl,pins = <IMX8QXP_UART1_RX_LSIO_GPIO0_IO22 0x21>, /* SODIMM 30 */
+ <IMX8QXP_UART1_TX_LSIO_GPIO0_IO21 0x4000021>; /* SODIMM 28 */
+ };
+
+ /* Atmel MXT touchsceen + boards with built-in Capacitive Touch Connector */
+ pinctrl_atmel_conn: atmelconnectorgrp {
+ fsl,pins = <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x4000021>, /* SODIMM 107 */
+ <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x21>; /* SODIMM 106 */
+ };
+
pinctrl_can_int: canintgrp {
fsl,pins = <IMX8QXP_QSPI0A_DQS_LSIO_GPIO3_IO13 0x40>; /* SODIMM 73 */
};
@@ -214,12 +230,10 @@ pinctrl_hog0: hog0grp {
<IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
<IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
- <IMX8QXP_QSPI0B_DATA2_LSIO_GPIO3_IO20 0x20>, /* SODIMM 107 */
<IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
<IMX8QXP_QSPI0B_DQS_LSIO_GPIO3_IO22 0x20>, /* SODIMM 102 */
<IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
<IMX8QXP_QSPI0B_SS0_B_LSIO_GPIO3_IO23 0x20>, /* SODIMM 104 */
- <IMX8QXP_QSPI0B_SS1_B_LSIO_GPIO3_IO24 0x20>, /* SODIMM 106 */
<IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
<IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
<IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 06/25] arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (4 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 05/25] arm64: dts: colibri-imx8x: Add atmel pinctrl groups Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 07/25] arm64: dts: colibri-imx8x: Split pinctrl_hog1 Philippe Schenker
` (18 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add missing pinctrl groups that can be used to enable the correct
muxing if csi_mclk is needed on SODIMM 75.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 0b84b65c846a..e1b907b7a85d 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -159,6 +159,10 @@ pinctrl_csi_ctl: csictlgrp {
<IMX8QXP_QSPI0A_SS1_B_LSIO_GPIO3_IO15 0x20>; /* SODIMM 89 */
};
+ pinctrl_csi_mclk: csimclkgrp {
+ fsl,pins = <IMX8QXP_CSI_MCLK_CI_PI_MCLK 0xC0000041>; /* SODIMM 75 / X3-12 */
+ };
+
pinctrl_ext_io0: extio0grp {
fsl,pins = <IMX8QXP_ENET0_RGMII_RXD3_LSIO_GPIO5_IO08 0x06000040>; /* SODIMM 135 */
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 07/25] arm64: dts: colibri-imx8x: Split pinctrl_hog1
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (5 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 06/25] arm64: dts: colibri-imx8x: Add pinctrl group for csi_mclk Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 08/25] arm64: dts: colibri-imx8x: Correct pull on lcdif Philippe Schenker
` (17 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Split pinctrl_hog1 into a second group so CSI_MCLK can be muxed to a
gpio on its own.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index e1b907b7a85d..432449359625 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -119,7 +119,8 @@ &usdhc2 {
&iomuxc {
pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>;
+ pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
+ <&pinctrl_hog2>;
/* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp {
@@ -253,6 +254,10 @@ pinctrl_hog1: hog1grp {
<IMX8QXP_QSPI0A_SCLK_LSIO_GPIO3_IO16 0x20>; /* SODIMM 93 */
};
+ pinctrl_hog2: hog2grp {
+ fsl,pins = <IMX8QXP_CSI_MCLK_LSIO_GPIO3_IO01 0x20>; /* SODIMM 75 */
+ };
+
/*
* This pin is used in the SCFW as a UART. Using it from
* Linux would require rewritting the SCFW board file.
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 08/25] arm64: dts: colibri-imx8x: Correct pull on lcdif
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (6 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 07/25] arm64: dts: colibri-imx8x: Split pinctrl_hog1 Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 09/25] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2 Philippe Schenker
` (16 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
The pads USDHC1_RESET_B and MCLK_IN1 need a pull-down instead of
pull-disabled. Correct this.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 432449359625..d4d748a93afc 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -304,7 +304,7 @@ pinctrl_lcdif: lcdifgrp {
<IMX8QXP_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x60>, /* SODIMM 62 */
<IMX8QXP_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x60>, /* SODIMM 48 */
<IMX8QXP_MCLK_IN0_ADMA_LCDIF_VSYNC 0x60>, /* SODIMM 82 */
- <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x60>, /* SODIMM 44 */
+ <IMX8QXP_MCLK_IN1_ADMA_LCDIF_EN 0x40>, /* SODIMM 44 */
<IMX8QXP_MCLK_OUT0_ADMA_LCDIF_CLK 0x60>, /* SODIMM 56 */
<IMX8QXP_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x60>, /* SODIMM 52 */
<IMX8QXP_SPDIF0_RX_ADMA_LCDIF_D10 0x60>, /* SODIMM 74 */
@@ -315,7 +315,7 @@ pinctrl_lcdif: lcdifgrp {
<IMX8QXP_SPI3_SDI_ADMA_LCDIF_D15 0x60>, /* SODIMM 64 */
<IMX8QXP_SPI3_SDO_ADMA_LCDIF_D14 0x60>, /* SODIMM 66 */
<IMX8QXP_UART1_CTS_B_ADMA_LCDIF_D17 0x60>, /* SODIMM 61 */
- <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x60>, /* SODIMM 44 */
+ <IMX8QXP_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x40>, /* SODIMM 44 */
<IMX8QXP_USDHC1_WP_LSIO_GPIO4_IO21 0x60>; /* SODIMM 76 */
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 09/25] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (7 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 08/25] arm64: dts: colibri-imx8x: Correct pull on lcdif Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 10/25] arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd Philippe Schenker
` (15 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add a separate pinctrl group for chip-select 2 for Colibri SPI. That way
one is able to use it separately.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index d4d748a93afc..2cc94589c36f 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -120,7 +120,7 @@ &usdhc2 {
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
- <&pinctrl_hog2>;
+ <&pinctrl_hog2>, <&pinctrl_lpspi2_cs2>;
/* On-module touch pen-down interrupt */
pinctrl_ad7879_int: ad7879intgrp {
@@ -231,7 +231,6 @@ pinctrl_hog0: hog0grp {
<IMX8QXP_CSI_D07_CI_PI_D09 0x61>, /* SODIMM 65 */
<IMX8QXP_CSI_PCLK_LSIO_GPIO3_IO00 0x20>, /* SODIMM 96 */
<IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
- <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x06000020>, /* SODIMM 65 */
<IMX8QXP_QSPI0A_DATA2_LSIO_GPIO3_IO11 0x20>, /* SODIMM 69 */
<IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>, /* SODIMM 99 */
<IMX8QXP_QSPI0B_DATA1_LSIO_GPIO3_IO19 0x20>, /* SODIMM 105 */
@@ -327,6 +326,10 @@ pinctrl_lpspi2: lpspi2grp {
<IMX8QXP_SPI2_SDO_ADMA_SPI2_SDO 0x06000040>; /* SODIMM 92 */
};
+ pinctrl_lpspi2_cs2: lpspi2cs2grp {
+ fsl,pins = <IMX8QXP_ENET0_RGMII_TXD3_LSIO_GPIO5_IO02 0x21>; /* SODIMM 65 */
+ };
+
/* Colibri UART_B */
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <IMX8QXP_FLEXCAN0_RX_ADMA_UART0_RTS_B 0x06000020>, /* SODIMM 34 */
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 10/25] arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (8 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 09/25] arm64: dts: colibri-imx8x: Add separate pinctrl group for cs2 Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 11/25] arm64: dts: colibri-imx8x: Sort fec1 node alphabetically Philippe Schenker
` (14 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
The colibri imx8x contains a dedicated gpio meant for HDMI
hot-plug-detect. Add a pinctrl group to make this usable.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 2cc94589c36f..c6aaf6aeab07 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -218,6 +218,11 @@ pinctrl_gpio_bl_on: gpioblongrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA3_LSIO_GPIO3_IO12 0x60>; /* SODIMM 71 */
};
+ /* HDMI Hot Plug Detect on FFC (X2) */
+ pinctrl_gpio_hpd: gpiohpdgrp {
+ fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_00_LSIO_GPIO1_IO31 0x20>; /* SODIMM 138 */
+ };
+
pinctrl_gpiokeys: gpiokeysgrp {
fsl,pins = <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 11/25] arm64: dts: colibri-imx8x: Sort fec1 node alphabetically
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (9 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 10/25] arm64: dts: colibri-imx8x: Add pinctrl group for hdmi hpd Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 12/25] arm64: dts: colibri-imx8x: Add SPI Philippe Schenker
` (13 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
fec1 seems to be the only one that is not properly sorted
alphabetically. Put it to the location it belongs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../dts/freescale/imx8x-colibri-eval-v3.dtsi | 10 ++---
.../boot/dts/freescale/imx8x-colibri.dtsi | 42 +++++++++----------
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index dc0339b35a3c..870375301243 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -26,6 +26,11 @@ key-wakeup {
};
};
+/* Colibri FastEthernet */
+&fec1 {
+ status = "okay";
+};
+
&i2c1 {
status = "okay";
@@ -51,11 +56,6 @@ &lpuart3 {
status = "okay";
};
-/* Colibri FastEthernet */
-&fec1 {
- status = "okay";
-};
-
/* Colibri SD/MMC Card */
&usdhc2 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index c6aaf6aeab07..31c771c1b788 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -16,6 +16,27 @@ reg_module_3v3: regulator-module-3v3 {
};
};
+/* Colibri FastEthernet */
+&fec1 {
+ pinctrl-names = "default", "sleep";
+ pinctrl-0 = <&pinctrl_fec1>;
+ pinctrl-1 = <&pinctrl_fec1_sleep>;
+ fsl,magic-packet;
+ phy-handle = <ðphy0>;
+ phy-mode = "rmii";
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethphy0: ethernet-phy@2 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <2>;
+ max-speed = <100>;
+ };
+ };
+};
+
/* On-module I2C */
&i2c0 {
#address-cells = <1>;
@@ -70,27 +91,6 @@ &lpuart3 {
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};
-/* Colibri FastEthernet */
-&fec1 {
- pinctrl-names = "default", "sleep";
- pinctrl-0 = <&pinctrl_fec1>;
- pinctrl-1 = <&pinctrl_fec1_sleep>;
- fsl,magic-packet;
- phy-handle = <ðphy0>;
- phy-mode = "rmii";
-
- mdio {
- #address-cells = <1>;
- #size-cells = <0>;
-
- ethphy0: ethernet-phy@2 {
- compatible = "ethernet-phy-ieee802.3-c22";
- reg = <2>;
- max-speed = <100>;
- };
- };
-};
-
/* On-module eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 12/25] arm64: dts: colibri-imx8x: Add SPI
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (10 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 11/25] arm64: dts: colibri-imx8x: Sort fec1 node alphabetically Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 13/25] arm64: dts: colibri-imx8x: Add gpio-line-names Philippe Schenker
` (12 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add Colibri SPI to the board. lpspi2 is being exposed on the SoM edge.
Add settings to the module-level but finally enable it on the eval-board
dtsi.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi | 5 +++++
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 7 +++++++
2 files changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index 870375301243..77222d76bd95 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -41,6 +41,11 @@ rtc_i2c: rtc@68 {
};
};
+/* Colibri SPI */
+&lpspi2 {
+ status = "okay";
+};
+
/* Colibri UART_B */
&lpuart0 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 31c771c1b788..cfa2c569e01c 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -91,6 +91,13 @@ &lpuart3 {
pinctrl-0 = <&pinctrl_lpuart3>, <&pinctrl_lpuart3_ctrl>;
};
+/* Colibri SPI */
+&lpspi2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lpspi2>;
+ cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
+};
+
/* On-module eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 13/25] arm64: dts: colibri-imx8x: Add gpio-line-names
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (11 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 12/25] arm64: dts: colibri-imx8x: Add SPI Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 14/25] arm64: dts: colibri-imx8x: Disable touchscreen by default Philippe Schenker
` (11 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
This commit adds gpio-line-names in line with other SoM from Toradex.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../boot/dts/freescale/imx8x-colibri.dtsi | 152 ++++++++++++++++++
1 file changed, 152 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index cfa2c569e01c..9555cfa8b27e 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -98,6 +98,158 @@ &lpspi2 {
cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>;
};
+&lsio_gpio0 {
+ gpio-line-names = "",
+ "SODIMM_70",
+ "SODIMM_60",
+ "SODIMM_58",
+ "SODIMM_78",
+ "SODIMM_72",
+ "SODIMM_80",
+ "SODIMM_46",
+ "SODIMM_62",
+ "SODIMM_48",
+ "SODIMM_74",
+ "SODIMM_50",
+ "SODIMM_52",
+ "SODIMM_54",
+ "SODIMM_66",
+ "SODIMM_64",
+ "SODIMM_68",
+ "",
+ "",
+ "SODIMM_82",
+ "SODIMM_56",
+ "SODIMM_28",
+ "SODIMM_30",
+ "",
+ "SODIMM_61",
+ "SODIMM_103",
+ "",
+ "",
+ "",
+ "SODIMM_25",
+ "SODIMM_27",
+ "SODIMM_100";
+};
+
+&lsio_gpio1 {
+ gpio-line-names = "SODIMM_86",
+ "SODIMM_92",
+ "SODIMM_90",
+ "SODIMM_88",
+ "",
+ "",
+ "",
+ "SODIMM_59",
+ "",
+ "SODIMM_6",
+ "SODIMM_8",
+ "",
+ "",
+ "SODIMM_2",
+ "SODIMM_4",
+ "SODIMM_34",
+ "SODIMM_32",
+ "SODIMM_63",
+ "SODIMM_55",
+ "SODIMM_33",
+ "SODIMM_35",
+ "SODIMM_36",
+ "SODIMM_38",
+ "SODIMM_21",
+ "SODIMM_19",
+ "SODIMM_140",
+ "SODIMM_142",
+ "SODIMM_196",
+ "SODIMM_194",
+ "SODIMM_186",
+ "SODIMM_188",
+ "SODIMM_138";
+};
+
+&lsio_gpio2 {
+ gpio-line-names = "SODIMM_23",
+ "",
+ "",
+ "SODIMM_144";
+};
+
+&lsio_gpio3 {
+ gpio-line-names = "SODIMM_96",
+ "SODIMM_75",
+ "SODIMM_37",
+ "SODIMM_29",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_43",
+ "SODIMM_45",
+ "SODIMM_69",
+ "SODIMM_71",
+ "SODIMM_73",
+ "SODIMM_77",
+ "SODIMM_89",
+ "SODIMM_93",
+ "SODIMM_95",
+ "SODIMM_99",
+ "SODIMM_105",
+ "SODIMM_107",
+ "SODIMM_98",
+ "SODIMM_102",
+ "SODIMM_104",
+ "SODIMM_106";
+};
+
+&lsio_gpio4 {
+ gpio-line-names = "",
+ "",
+ "",
+ "SODIMM_129",
+ "SODIMM_133",
+ "SODIMM_127",
+ "SODIMM_131",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_44",
+ "",
+ "SODIMM_76",
+ "SODIMM_31",
+ "SODIMM_47",
+ "SODIMM_190",
+ "SODIMM_192",
+ "SODIMM_49",
+ "SODIMM_51",
+ "SODIMM_53";
+};
+
+&lsio_gpio5 {
+ gpio-line-names = "",
+ "SODIMM_57",
+ "SODIMM_65",
+ "SODIMM_85",
+ "",
+ "",
+ "",
+ "",
+ "SODIMM_135",
+ "SODIMM_137",
+ "UNUSABLE_SODIMM_180",
+ "UNUSABLE_SODIMM_184";
+};
+
/* On-module eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 14/25] arm64: dts: colibri-imx8x: Disable touchscreen by default
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (12 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 13/25] arm64: dts: colibri-imx8x: Add gpio-line-names Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 15/25] arm64: dts: colibri-imx8x: Add jpegenc/dec Philippe Schenker
` (10 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Do not enable the touchscreen. By default it is not used but should be
kept to enable it from a file that includes imx8x-colibri.dtsi.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 9555cfa8b27e..0e8448aa373e 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -61,6 +61,7 @@ touchscreen@2c {
adi,median-filter-size = /bits/ 8 <2>;
adi,resistance-plate-x = <120>;
touchscreen-max-pressure = <4096>;
+ status = "disabled";
};
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 15/25] arm64: dts: colibri-imx8x: Add jpegenc/dec
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (13 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 14/25] arm64: dts: colibri-imx8x: Disable touchscreen by default Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 16/25] arm64: dts: colibri-imx8x: Add colibri pwm b, c, d Philippe Schenker
` (9 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
jpeg encoder and decoder are available. Do enable them in the module
level device-tree since those are self-contained.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 0e8448aa373e..b849b378b017 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -74,6 +74,14 @@ &i2c1 {
clock-frequency = <100000>;
};
+&jpegdec {
+ status = "okay";
+};
+
+&jpegenc {
+ status = "okay";
+};
+
/* Colibri UART_B */
&lpuart0 {
pinctrl-names = "default";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 16/25] arm64: dts: colibri-imx8x: Add colibri pwm b, c, d
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (14 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 15/25] arm64: dts: colibri-imx8x: Add jpegenc/dec Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can Philippe Schenker
` (8 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add Colibri PWM_B, PWM_C, PWM_D to the module-level device-tree and set
the status to ok on the eval-board.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../dts/freescale/imx8x-colibri-eval-v3.dtsi | 15 +++++++++++++
.../boot/dts/freescale/imx8x-colibri.dtsi | 21 +++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index 77222d76bd95..625d2caaf5d1 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -56,6 +56,21 @@ &lpuart2 {
status = "okay";
};
+/* Colibri PWM_B */
+&lsio_pwm0 {
+ status = "okay";
+};
+
+/* Colibri PWM_C */
+&lsio_pwm1 {
+ status = "okay";
+};
+
+/* Colibri PWM_D */
+&lsio_pwm2 {
+ status = "okay";
+};
+
/* Colibri UART_A */
&lpuart3 {
status = "okay";
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index b849b378b017..180a1d940b8d 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -259,6 +259,27 @@ &lsio_gpio5 {
"UNUSABLE_SODIMM_184";
};
+/* Colibri PWM_B */
+&lsio_pwm0 {
+ #pwm-cells = <3>;
+ pinctrl-0 = <&pinctrl_pwm_b>;
+ pinctrl-names = "default";
+};
+
+/* Colibri PWM_C */
+&lsio_pwm1 {
+ #pwm-cells = <3>;
+ pinctrl-0 = <&pinctrl_pwm_c>;
+ pinctrl-names = "default";
+};
+
+/* Colibri PWM_D */
+&lsio_pwm2 {
+ #pwm-cells = <3>;
+ pinctrl-0 = <&pinctrl_pwm_d>;
+ pinctrl-names = "default";
+};
+
/* On-module eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (15 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 16/25] arm64: dts: colibri-imx8x: Add colibri pwm b, c, d Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 13:00 ` Krzysztof Kozlowski
2023-03-08 12:52 ` [PATCH v1 18/25] arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card Philippe Schenker
` (7 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add mcp2515 spi-to-can to &lpspi2.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../dts/freescale/imx8x-colibri-eval-v3.dtsi | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index 625d2caaf5d1..e7e3cf462408 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -11,6 +11,13 @@ aliases {
rtc1 = &rtc;
};
+ /* fixed crystal dedicated to mcp25xx */
+ clk16m: clock-16mhz-fixed {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <16000000>;
+ };
+
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
@@ -44,6 +51,18 @@ rtc_i2c: rtc@68 {
/* Colibri SPI */
&lpspi2 {
status = "okay";
+
+ mcp2515: can@0 {
+ compatible = "microchip,mcp2515";
+ reg = <0>;
+ interrupt-parent = <&lsio_gpio3>;
+ interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
+ pinctrl-0 = <&pinctrl_can_int>;
+ pinctrl-names = "default";
+ clocks = <&clk16m>;
+ spi-max-frequency = <10000000>;
+ status = "okay";
+ };
};
/* Colibri UART_B */
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 12:52 ` [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can Philippe Schenker
@ 2023-03-08 13:00 ` Krzysztof Kozlowski
2023-03-08 13:43 ` Philippe Schenker
2023-03-08 14:12 ` Philippe Schenker
0 siblings, 2 replies; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 13:00 UTC (permalink / raw)
To: Philippe Schenker, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
On 08/03/2023 13:52, Philippe Schenker wrote:
> From: Philippe Schenker <philippe.schenker@toradex.com>
>
> Add mcp2515 spi-to-can to &lpspi2.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> ---
>
> .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 19 +++++++++++++++++++
> 1 file changed, 19 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> index 625d2caaf5d1..e7e3cf462408 100644
> --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
There is no such file.
> @@ -11,6 +11,13 @@ aliases {
> rtc1 = &rtc;
> };
>
> + /* fixed crystal dedicated to mcp25xx */
> + clk16m: clock-16mhz-fixed {
Drop "fixed".
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <16000000>;
> + };
> +
> gpio-keys {
> compatible = "gpio-keys";
> pinctrl-names = "default";
> @@ -44,6 +51,18 @@ rtc_i2c: rtc@68 {
> /* Colibri SPI */
> &lpspi2 {
> status = "okay";
> +
> + mcp2515: can@0 {
> + compatible = "microchip,mcp2515";
> + reg = <0>;
> + interrupt-parent = <&lsio_gpio3>;
> + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> + pinctrl-0 = <&pinctrl_can_int>;
> + pinctrl-names = "default";
> + clocks = <&clk16m>;
You just sorted all nodes in previous patches and add something
unsorted? What is then the style of order? Random name?
> + spi-max-frequency = <10000000>;
> + status = "okay";
Why do you need it?
> + };
> };
>
> /* Colibri UART_B */
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 13:00 ` Krzysztof Kozlowski
@ 2023-03-08 13:43 ` Philippe Schenker
2023-03-08 14:34 ` Krzysztof Kozlowski
2023-03-08 14:12 ` Philippe Schenker
1 sibling, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 13:43 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On Wed, 2023-03-08 at 14:00 +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 13:52, Philippe Schenker wrote:
> > From: Philippe Schenker <philippe.schenker@toradex.com>
> >
> > Add mcp2515 spi-to-can to &lpspi2.
> >
> > Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> > ---
> >
> > .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 19
> > +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-
> > v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> > index 625d2caaf5d1..e7e3cf462408 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
>
> There is no such file.
Thanks for your feedback!
This file is being created int he first patch in the series.
>
> > @@ -11,6 +11,13 @@ aliases {
> > rtc1 = &rtc;
> > };
> >
> > + /* fixed crystal dedicated to mcp25xx */
> > + clk16m: clock-16mhz-fixed {
>
> Drop "fixed".
I'll prepare a v2 and plan to send it out beginning of next week.
>
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <16000000>;
> > + };
> > +
> > gpio-keys {
> > compatible = "gpio-keys";
> > pinctrl-names = "default";
> > @@ -44,6 +51,18 @@ rtc_i2c: rtc@68 {
> > /* Colibri SPI */
> > &lpspi2 {
> > status = "okay";
> > +
> > + mcp2515: can@0 {
> > + compatible = "microchip,mcp2515";
> > + reg = <0>;
> > + interrupt-parent = <&lsio_gpio3>;
> > + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> > + pinctrl-0 = <&pinctrl_can_int>;
> > + pinctrl-names = "default";
> > + clocks = <&clk16m>;
>
> You just sorted all nodes in previous patches and add something
> unsorted? What is then the style of order? Random name?
My logic behind this one is
1. compatible property
2. reg property
3. standard properties
- first interrupt
- then pinctrl
4. specific properties
- again alphabetically: clocks, spi-max-frequency
5. status
How would you do it?
>
> > + spi-max-frequency = <10000000>;
> > + status = "okay";
>
> Why do you need it?
This chip is placed on our eval-board and we usually try to enable it so
someone can right away use CAN.
>
> > + };
> > };
> >
> > /* Colibri UART_B */
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 13:43 ` Philippe Schenker
@ 2023-03-08 14:34 ` Krzysztof Kozlowski
2023-03-08 14:46 ` Philippe Schenker
0 siblings, 1 reply; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 14:34 UTC (permalink / raw)
To: dev, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On 08/03/2023 14:43, Philippe Schenker wrote:
>>> + mcp2515: can@0 {
>>> + compatible = "microchip,mcp2515";
>>> + reg = <0>;
>>> + interrupt-parent = <&lsio_gpio3>;
>>> + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
>>> + pinctrl-0 = <&pinctrl_can_int>;
>>> + pinctrl-names = "default";
>>> + clocks = <&clk16m>;
>>
>> You just sorted all nodes in previous patches and add something
>> unsorted? What is then the style of order? Random name?
>
> My logic behind this one is
>
> 1. compatible property
> 2. reg property
> 3. standard properties
> - first interrupt
> - then pinctrl
> 4. specific properties
> - again alphabetically: clocks, spi-max-frequency
clocks and spi-max-frequency are standard properties.
BTW, what is a specific property?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread* Re: [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 14:34 ` Krzysztof Kozlowski
@ 2023-03-08 14:46 ` Philippe Schenker
0 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 14:46 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, linux-kernel
On Wed, 2023-03-08 at 15:34 +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 14:43, Philippe Schenker wrote:
> > > > + mcp2515: can@0 {
> > > > + compatible = "microchip,mcp2515";
> > > > + reg = <0>;
> > > > + interrupt-parent = <&lsio_gpio3>;
> > > > + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> > > > + pinctrl-0 = <&pinctrl_can_int>;
> > > > + pinctrl-names = "default";
> > > > + clocks = <&clk16m>;
> > >
> > > You just sorted all nodes in previous patches and add something
> > > unsorted? What is then the style of order? Random name?
> >
> > My logic behind this one is
> >
> > 1. compatible property
> > 2. reg property
> > 3. standard properties
> > - first interrupt
> > - then pinctrl
> > 4. specific properties
> > - again alphabetically: clocks, spi-max-frequency
>
> clocks and spi-max-frequency are standard properties.
>
> BTW, what is a specific property?
I mean specific to this driver. With standard properties I mean those
you can add everywhere like pinctrl, interrupts etc. But then yes I
agree you can pretty quickly start to argue...
Would in this particular case something like
mcp2515: can@0 {
compatible = "microchip,mcp2515";
reg = <0>;
pinctrl-0 = <&pinctrl_can_int>;
pinctrl-names = "default";
clocks = <&clk16m>;
interrupt-parent = <&lsio_gpio3>;
interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
spi-max-frequency = <10000000>;
};
be better?
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* Re: [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can
2023-03-08 13:00 ` Krzysztof Kozlowski
2023-03-08 13:43 ` Philippe Schenker
@ 2023-03-08 14:12 ` Philippe Schenker
1 sibling, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 14:12 UTC (permalink / raw)
To: Krzysztof Kozlowski, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
On Wed, 2023-03-08 at 14:00 +0100, Krzysztof Kozlowski wrote:
> On 08/03/2023 13:52, Philippe Schenker wrote:
> > From: Philippe Schenker <philippe.schenker@toradex.com>
> >
> > Add mcp2515 spi-to-can to &lpspi2.
> >
> > Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> > ---
> >
> > .../dts/freescale/imx8x-colibri-eval-v3.dtsi | 19
> > +++++++++++++++++++
> > 1 file changed, 19 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-
> > v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> > index 625d2caaf5d1..e7e3cf462408 100644
> > --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
> > +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
>
> There is no such file.
>
> > @@ -11,6 +11,13 @@ aliases {
> > rtc1 = &rtc;
> > };
> >
> > + /* fixed crystal dedicated to mcp25xx */
> > + clk16m: clock-16mhz-fixed {
>
> Drop "fixed".
>
> > + compatible = "fixed-clock";
> > + #clock-cells = <0>;
> > + clock-frequency = <16000000>;
> > + };
> > +
> > gpio-keys {
> > compatible = "gpio-keys";
> > pinctrl-names = "default";
> > @@ -44,6 +51,18 @@ rtc_i2c: rtc@68 {
> > /* Colibri SPI */
> > &lpspi2 {
> > status = "okay";
> > +
> > + mcp2515: can@0 {
> > + compatible = "microchip,mcp2515";
> > + reg = <0>;
> > + interrupt-parent = <&lsio_gpio3>;
> > + interrupts = <13 IRQ_TYPE_EDGE_FALLING>;
> > + pinctrl-0 = <&pinctrl_can_int>;
> > + pinctrl-names = "default";
> > + clocks = <&clk16m>;
>
> You just sorted all nodes in previous patches and add something
> unsorted? What is then the style of order? Random name?
>
> > + spi-max-frequency = <10000000>;
> > + status = "okay";
>
> Why do you need it?
Ok, now I know what you mean. Will remove it in v2.
>
> > + };
> > };
> >
> > /* Colibri UART_B */
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v1 18/25] arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (16 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 17/25] arm64: dts: colibri-imx8x: eval: Add spi-to-can Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 19/25] arm64: dts: colibri-imx8x: Set thermal thresholds Philippe Schenker
` (6 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Many Colibri carrier boards are using 3.3V pull-up resistors on the
SD-Card connector. Letting it switch to 1.8V is an invalid state.
Do prevent this from happening by keeping the signaling voltage at 3.3V.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 180a1d940b8d..f09a6aad6275 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -303,6 +303,7 @@ &usdhc2 {
bus-width = <4>;
cd-gpios = <&lsio_gpio3 9 GPIO_ACTIVE_LOW>;
disable-wp;
+ no-1-8-v;
vmmc-supply = <®_module_3v3>;
};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 19/25] arm64: dts: colibri-imx8x: Set thermal thresholds
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (17 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 18/25] arm64: dts: colibri-imx8x: Add no-1-8-v to sd-card Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 20/25] arm64: dts: colibri-imx8x: Move gpio-keys to som level Philippe Schenker
` (5 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Set critical/alert thermal thresholds for all relevant SOC
temperature trips to the IT value (max T_junction 105 degree
Celsius) in accordance with the IT grade of the SOM.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index f09a6aad6275..2f86a2eb4ff3 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -16,6 +16,18 @@ reg_module_3v3: regulator-module-3v3 {
};
};
+&cpu_alert0 {
+ hysteresis = <2000>;
+ temperature = <90000>;
+ type = "passive";
+};
+
+&cpu_crit0 {
+ hysteresis = <2000>;
+ temperature = <105000>;
+ type = "critical";
+};
+
/* Colibri FastEthernet */
&fec1 {
pinctrl-names = "default", "sleep";
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 20/25] arm64: dts: colibri-imx8x: Move gpio-keys to som level
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (18 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 19/25] arm64: dts: colibri-imx8x: Set thermal thresholds Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 21/25] arm64: dts: colibri-imx8x: Add todo comments Philippe Schenker
` (4 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
SODIMM_45 that is connected to "&lsio_gpio3 10" is defined in the
Colibri standard to be a wakeup pin.
Move this to the SoM level device-tree and keep it disabled by default
but do enable it again on the carrier-board.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../dts/freescale/imx8x-colibri-eval-v3.dtsi | 16 +++-------------
arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi | 15 +++++++++++++++
2 files changed, 18 insertions(+), 13 deletions(-)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
index e7e3cf462408..8dfcb2cfdb68 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-eval-v3.dtsi
@@ -17,20 +17,10 @@ clk16m: clock-16mhz-fixed {
#clock-cells = <0>;
clock-frequency = <16000000>;
};
+};
- gpio-keys {
- compatible = "gpio-keys";
- pinctrl-names = "default";
- pinctrl-0 = <&pinctrl_gpiokeys>;
-
- key-wakeup {
- label = "Wake-Up";
- gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
- linux,code = <KEY_WAKEUP>;
- debounce-interval = <10>;
- wakeup-source;
- };
- };
+&colibri_gpio_keys {
+ status = "okay";
};
/* Colibri FastEthernet */
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index 2f86a2eb4ff3..e93e22c4053b 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -8,6 +8,21 @@ chosen {
stdout-path = &lpuart3;
};
+ colibri_gpio_keys: gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpiokeys>;
+ status = "disabled";
+
+ key-wakeup {
+ debounce-interval = <10>;
+ gpios = <&lsio_gpio3 10 GPIO_ACTIVE_HIGH>;
+ label = "Wake-Up";
+ linux,code = <KEY_WAKEUP>;
+ wakeup-source;
+ };
+ };
+
reg_module_3v3: regulator-module-3v3 {
compatible = "regulator-fixed";
regulator-max-microvolt = <3300000>;
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 21/25] arm64: dts: colibri-imx8x: Add todo comments
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (19 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 20/25] arm64: dts: colibri-imx8x: Move gpio-keys to som level Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 22/25] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards Philippe Schenker
` (3 subsequent siblings)
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Highlight what is still missing.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
.../boot/dts/freescale/imx8x-colibri.dtsi | 28 +++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
index e93e22c4053b..f70ab4db92ed 100644
--- a/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri.dtsi
@@ -31,6 +31,10 @@ reg_module_3v3: regulator-module-3v3 {
};
};
+/* TODO Analogue Inputs */
+
+/* TODO Cooling maps for DX */
+
&cpu_alert0 {
hysteresis = <2000>;
temperature = <90000>;
@@ -64,6 +68,10 @@ ethphy0: ethernet-phy@2 {
};
};
+/* TODO flexcan1 - 3 */
+
+/* TODO GPU */
+
/* On-module I2C */
&i2c0 {
#address-cells = <1>;
@@ -92,6 +100,10 @@ touchscreen@2c {
};
};
+/* TODO i2c lvds0 accessible on FFC (X2) */
+
+/* TODO i2c lvds1 accessible on FFC (X3) */
+
/* Colibri I2C */
&i2c1 {
#address-cells = <1>;
@@ -109,6 +121,8 @@ &jpegenc {
status = "okay";
};
+/* TODO Parallel RRB */
+
/* Colibri UART_B */
&lpuart0 {
pinctrl-names = "default";
@@ -307,6 +321,14 @@ &lsio_pwm2 {
pinctrl-names = "default";
};
+/* TODO MIPI CSI */
+
+/* TODO MIPI DSI with DSI-to-HDMI bridge lt8912 */
+
+/* TODO on-module PCIe for Wi-Fi */
+
+/* TODO On-module i2s / Audio */
+
/* On-module eMMC */
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
@@ -334,6 +356,12 @@ &usdhc2 {
vmmc-supply = <®_module_3v3>;
};
+/* TODO USB Client/Host */
+
+/* TODO USB Host */
+
+/* TODO VPU Encoder/Decoder */
+
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ext_io0>, <&pinctrl_hog0>, <&pinctrl_hog1>,
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 22/25] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (20 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 21/25] arm64: dts: colibri-imx8x: Add todo comments Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 13:04 ` Krzysztof Kozlowski
2023-03-08 12:52 ` [PATCH v1 23/25] arm64: dts: colibri-imx8x: Add aster carrier board Philippe Schenker
` (2 subsequent siblings)
24 siblings, 1 reply; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, Denys Drozdov, Fabio Estevam,
Frieder Schrempf, Li Yang, Marcel Ziswiler, Marek Vasut,
Matthias Schiffer, Max Krummenacher, Stefan Wahren, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Prepare the dt-bindings for the new colibri-imx8x carrier-boards Aster
and Iris.
The Toradex SoM standard is called Colibri, fix the typo.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
Documentation/devicetree/bindings/arm/fsl.yaml | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml
index 442ce8f4d675..6cb78c4ac614 100644
--- a/Documentation/devicetree/bindings/arm/fsl.yaml
+++ b/Documentation/devicetree/bindings/arm/fsl.yaml
@@ -1135,10 +1135,13 @@ properties:
- fsl,imx8dxl-evk # i.MX8DXL EVK Board
- const: fsl,imx8dxl
- - description: i.MX8QXP Boards with Toradex Coilbri iMX8X Modules
+ - description: i.MX8QXP Boards with Toradex Colibri iMX8X Modules
items:
- enum:
+ - toradex,colibri-imx8x-aster # Colibri iMX8X Module on Aster Board
- toradex,colibri-imx8x-eval-v3 # Colibri iMX8X Module on Colibri Evaluation Board V3
+ - toradex,colibri-imx8x-iris # Colibri iMX8X Module on Iris Board
+ - toradex,colibri-imx8x-iris-v2 # Colibri iMX8X Module on Iris Board V2
- const: toradex,colibri-imx8x
- const: fsl,imx8qxp
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* Re: [PATCH v1 22/25] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards
2023-03-08 12:52 ` [PATCH v1 22/25] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards Philippe Schenker
@ 2023-03-08 13:04 ` Krzysztof Kozlowski
0 siblings, 0 replies; 42+ messages in thread
From: Krzysztof Kozlowski @ 2023-03-08 13:04 UTC (permalink / raw)
To: Philippe Schenker, devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, Denys Drozdov, Fabio Estevam,
Frieder Schrempf, Li Yang, Marcel Ziswiler, Marek Vasut,
Matthias Schiffer, Max Krummenacher, Stefan Wahren, linux-kernel
On 08/03/2023 13:52, Philippe Schenker wrote:
> From: Philippe Schenker <philippe.schenker@toradex.com>
>
> Prepare the dt-bindings for the new colibri-imx8x carrier-boards Aster
> and Iris.
>
> The Toradex SoM standard is called Colibri, fix the typo.
>
> Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
> ---
>
> Documentation/devicetree/bindings/arm/fsl.yaml | 5 ++++-
> 1 file changed, 4 insertions(+), 1 deletion(-)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 42+ messages in thread
* [PATCH v1 23/25] arm64: dts: colibri-imx8x: Add aster carrier board
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (21 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 22/25] dt-bindings: arm: fsl: Add colibri-imx8x carrier boards Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 24/25] arm64: dts: colibri-imx8x: Add iris " Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 25/25] arm64: dts: colibri-imx8x: Add iris v2 " Philippe Schenker
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add the Toradex Aster Carrier Board for Colibri iMX8X, small form-factor
with header compatible with Arduino Uno and Raspberry Pi (RPi) maker
boards.
Additional details available at:
https://www.toradex.com/products/carrier-boards/aster-carrier-board
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8qxp-colibri-aster.dts | 16 +++++++
.../dts/freescale/imx8x-colibri-aster.dtsi | 44 +++++++++++++++++++
3 files changed, 61 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 836dcc501e6f..9f49e47589ab 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -129,6 +129,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.1.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-ixora-v1.2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
new file mode 100644
index 000000000000..966ecfb2a17e
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-aster.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-aster.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX8QXP on Aster Board";
+ compatible = "toradex,colibri-imx8x-aster",
+ "toradex,colibri-imx8x",
+ "fsl,imx8qxp";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
new file mode 100644
index 000000000000..aab655931cde
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-aster.dtsi
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+&colibri_gpio_keys {
+ status = "okay";
+};
+
+/* Colibri Ethernet */
+&fec1 {
+ status = "okay";
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_hog0>;
+};
+
+/* Colibri SPI */
+&lpspi2 {
+ cs-gpios = <&lsio_gpio1 0 GPIO_ACTIVE_LOW>,
+ <&lsio_gpio5 2 GPIO_ACTIVE_LOW>;
+};
+
+/* Colibri UART_B */
+&lpuart0 {
+ status = "okay";
+};
+
+/* Colibri UART_C */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&lpuart3 {
+ status= "okay";
+};
+
+/* Colibri SDCard */
+&usdhc2 {
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 24/25] arm64: dts: colibri-imx8x: Add iris carrier board
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (22 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 23/25] arm64: dts: colibri-imx8x: Add aster carrier board Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
2023-03-08 12:52 ` [PATCH v1 25/25] arm64: dts: colibri-imx8x: Add iris v2 " Philippe Schenker
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add the Toradex Iris Carrier Board for Colibri iMX8X, small form-factor
production ready board.
Additional details available at:
https://www.toradex.com/products/carrier-boards/iris-carrier-board
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8qxp-colibri-iris.dts | 16 +++
.../dts/freescale/imx8x-colibri-iris.dtsi | 115 ++++++++++++++++++
3 files changed, 132 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 9f49e47589ab..48bb0fe4a616 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -131,6 +131,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qm-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
new file mode 100644
index 000000000000..fed75b5d4a1c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-iris.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX8QXP on Colibri Iris Board";
+ compatible = "toradex,colibri-imx8x-iris",
+ "toradex,colibri-imx8x",
+ "fsl,imx8qxp";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
new file mode 100644
index 000000000000..5f30c88855e7
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris.dtsi
@@ -0,0 +1,115 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/ {
+ aliases {
+ rtc0 = &rtc_i2c;
+ rtc1 = &rtc;
+ };
+
+ reg_3v3: regulator-3v3 {
+ compatible = "regulator-fixed";
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3.3V";
+ };
+};
+
+&colibri_gpio_keys {
+ status = "okay";
+};
+
+/* Colibri FastEthernet */
+&fec1 {
+ status = "okay";
+};
+
+/* Colibri I2C */
+&i2c1 {
+ status = "okay";
+
+ /* M41T0M6 real time clock on carrier board */
+ rtc_i2c: rtc@68 {
+ compatible = "st,m41t0";
+ reg = <0x68>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_gpio_iris>;
+
+ pinctrl_gpio_iris: gpioirisgrp {
+ fsl,pins = <IMX8QXP_QSPI0B_DATA3_LSIO_GPIO3_IO21 0x20>, /* SODIMM 98 */
+ <IMX8QXP_USB_SS3_TC1_LSIO_GPIO4_IO04 0x20>, /* SODIMM 133 */
+ <IMX8QXP_SAI0_TXD_LSIO_GPIO0_IO25 0x20>, /* SODIMM 103 */
+ <IMX8QXP_SAI0_TXFS_LSIO_GPIO0_IO28 0x20>, /* SODIMM 101 */
+ <IMX8QXP_SAI0_RXD_LSIO_GPIO0_IO27 0x20>, /* SODIMM 97 */
+ <IMX8QXP_ENET0_RGMII_RXC_LSIO_GPIO5_IO03 0x06000020>, /* SODIMM 85 */
+ <IMX8QXP_SAI0_TXC_LSIO_GPIO0_IO26 0x20>, /* SODIMM 79 */
+ <IMX8QXP_QSPI0A_DATA1_LSIO_GPIO3_IO10 0x06700041>; /* SODIMM 45 */
+ };
+
+ pinctrl_uart1_forceoff: uart1forceoffgrp {
+ fsl,pins = <IMX8QXP_QSPI0A_SS0_B_LSIO_GPIO3_IO14 0x20>; /* SODIMM 22 */
+ };
+
+ pinctrl_uart23_forceoff: uart23forceoffgrp {
+ fsl,pins = <IMX8QXP_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x20>; /* SODIMM 23 */
+ };
+};
+
+/* Colibri SPI */
+&lpspi2 {
+ status = "okay";
+};
+
+/* Colibri UART_B */
+&lpuart0 {
+ status = "okay";
+};
+
+/* Colibri UART_C */
+&lpuart2 {
+ status = "okay";
+};
+
+/* Colibri UART_A */
+&lpuart3 {
+ status= "okay";
+};
+
+&lsio_gpio3 {
+ /*
+ * This turns the LVDS transceiver on. If one wants to turn the
+ * transceiver off, that property has to be deleted and the gpio handled
+ * in userspace.
+ */
+ lvds-tx-on-hog {
+ gpio-hog;
+ gpios = <18 0>;
+ output-high;
+ };
+};
+
+/* Colibri PWM_B */
+&lsio_pwm0 {
+ status = "okay";
+};
+
+/* Colibri PWM_C */
+&lsio_pwm1 {
+ status = "okay";
+};
+
+/* Colibri PWM_D */
+&lsio_pwm2 {
+ status = "okay";
+};
+
+/* Colibri SD/MMC Card */
+&usdhc2 {
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread* [PATCH v1 25/25] arm64: dts: colibri-imx8x: Add iris v2 carrier board
2023-03-08 12:52 [PATCH v1 00/25] Update Colibri iMX8X Devicetrees Philippe Schenker
` (23 preceding siblings ...)
2023-03-08 12:52 ` [PATCH v1 24/25] arm64: dts: colibri-imx8x: Add iris " Philippe Schenker
@ 2023-03-08 12:52 ` Philippe Schenker
24 siblings, 0 replies; 42+ messages in thread
From: Philippe Schenker @ 2023-03-08 12:52 UTC (permalink / raw)
To: devicetree, Shawn Guo, Sascha Hauer
Cc: NXP Linux Team, Krzysztof Kozlowski, Rob Herring,
Pengutronix Kernel Team, Frank Rowand, linux-arm-kernel,
Fabio Estevam, Philippe Schenker, linux-kernel
From: Philippe Schenker <philippe.schenker@toradex.com>
Add the Toradex Iris V2 Carrier Board for Colibri iMX8X, small form-factor
production ready board.
Additional details available at:
https://www.toradex.com/products/carrier-boards/iris-carrier-board
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
---
arch/arm64/boot/dts/freescale/Makefile | 1 +
.../dts/freescale/imx8qxp-colibri-iris-v2.dts | 16 +++++++
.../dts/freescale/imx8x-colibri-iris-v2.dtsi | 45 +++++++++++++++++++
3 files changed, 62 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
create mode 100644 arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile
index 48bb0fe4a616..2eb746f6a2c2 100644
--- a/arch/arm64/boot/dts/freescale/Makefile
+++ b/arch/arm64/boot/dts/freescale/Makefile
@@ -132,6 +132,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-ai_ml.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-aster.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-eval-v3.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris.dtb
+dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb
dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb
dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
new file mode 100644
index 000000000000..cca33213fa9b
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-colibri-iris-v2.dts
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+/dts-v1/;
+
+#include "imx8qxp-colibri.dtsi"
+#include "imx8x-colibri-iris-v2.dtsi"
+
+/ {
+ model = "Toradex Colibri iMX8QXP on Colibri Iris V2 Board";
+ compatible = "toradex,colibri-imx8x-iris-v2",
+ "toradex,colibri-imx8x",
+ "fsl,imx8qxp";
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
new file mode 100644
index 000000000000..98202a437040
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
+/*
+ * Copyright 2018-2021 Toradex
+ */
+
+#include "imx8x-colibri-iris.dtsi"
+
+/ {
+ reg_3v3_vmmc: regulator-3v3-vmmc {
+ compatible = "regulator-fixed";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_enable_3v3_vmmc>;
+ enable-active-high;
+ gpio = <&lsio_gpio0 31 GPIO_ACTIVE_HIGH>;
+ regulator-max-microvolt = <3300000>;
+ regulator-min-microvolt = <3300000>;
+ regulator-name = "3v3_vmmc";
+ startup-delay-us = <100>;
+ };
+};
+
+&iomuxc {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>;
+
+ pinctrl_enable_3v3_vmmc: enable_3v3_vmmc {
+ fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>; /* SODIMM 100 */
+ };
+
+ pinctrl_lvds_converter: lcd-lvds {
+ fsl,pins = <IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20>, /* SODIMM 55 */
+ /* 6B/8B mode. Select LOW - 8B mode (24bit) */
+ <IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20>, /* SODIMM 63 */
+ <IMX8QXP_QSPI0B_SCLK_LSIO_GPIO3_IO17 0x20>, /* SODIMM 95 */
+ <IMX8QXP_QSPI0B_DATA0_LSIO_GPIO3_IO18 0x20>; /* SODIMM 99 */
+ };
+};
+
+/* Colibri SD/MMC Card */
+&usdhc2 {
+ cap-power-off-card;
+ /delete-property/ no-1-8-v;
+ vmmc-supply = <®_3v3_vmmc>;
+ status = "okay";
+};
--
2.39.2
^ permalink raw reply related [flat|nested] 42+ messages in thread