* [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support
@ 2023-02-13 22:22 Frank Li
2023-02-13 22:22 ` [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
2023-03-14 0:50 ` [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Shawn Guo
0 siblings, 2 replies; 4+ messages in thread
From: Frank Li @ 2023-02-13 22:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
Cc: imx
There are cadence usb3.0 controller in 8qxp and 8qm.
Add usb3 node at common connect subsystem.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
.../boot/dts/freescale/imx8-ss-conn.dtsi | 72 +++++++++++++++++++
1 file changed, 72 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
index 4852760adeee..94692cee25a0 100644
--- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
@@ -138,6 +138,56 @@ fec2: ethernet@5b050000 {
status = "disabled";
};
+ usbotg3: usb@5b110000 {
+ compatible = "fsl,imx8qm-usb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0x5b110000 0x10000>;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
+ <&usb3_lpcg IMX_LPCG_CLK_0>,
+ <&usb3_lpcg IMX_LPCG_CLK_7>,
+ <&usb3_lpcg IMX_LPCG_CLK_4>,
+ <&usb3_lpcg IMX_LPCG_CLK_5>;
+ clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
+ "usb3_ipg_clk", "usb3_core_pclk";
+ assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ assigned-clock-rates = <125000000>, <12000000>, <250000000>;
+ power-domains = <&pd IMX_SC_R_USB_2>;
+ status = "disabled";
+
+ usbotg3_cdns3: usb@5b120000 {
+ compatible = "cdns,usb3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "host", "peripheral", "otg", "wakeup";
+ reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
+ <0x5b140000 0x10000>, /* memory area for DEVICE registers */
+ <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
+ reg-names = "xhci", "dev", "otg";
+ phys = <&usb3_phy>;
+ phy-names = "cdns3,usb3-phy";
+ status = "disabled";
+ };
+ };
+
+ usb3_phy: usb-phy@5b160000 {
+ compatible = "nxp,salvo-phy";
+ reg = <0x5b160000 0x40000>;
+ clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
+ clock-names = "salvo_phy_clk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
/* LPCG clocks */
sdhc0_lpcg: clock-controller@5b200000 {
compatible = "fsl,imx8qxp-lpcg";
@@ -234,4 +284,26 @@ usb2_lpcg: clock-controller@5b270000 {
clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
power-domains = <&pd IMX_SC_R_USB_0_PHY>;
};
+
+ usb3_lpcg: clock-controller@5b280000 {
+ compatible = "fsl,imx8qxp-lpcg";
+ reg = <0x5b280000 0x10000>;
+ #clock-cells = <1>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
+ <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
+ <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
+ clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&conn_ipg_clk>,
+ <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
+ clock-output-names = "usb3_app_clk",
+ "usb3_lpm_clk",
+ "usb3_ipg_clk",
+ "usb3_core_pclk",
+ "usb3_phy_clk",
+ "usb3_aclk";
+ power-domains = <&pd IMX_SC_R_USB_2_PHY>;
+ };
};
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
2023-02-13 22:22 [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Frank Li
@ 2023-02-13 22:22 ` Frank Li
2023-03-14 0:53 ` Shawn Guo
2023-03-14 0:50 ` [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Shawn Guo
1 sibling, 1 reply; 4+ messages in thread
From: Frank Li @ 2023-02-13 22:22 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Shawn Guo, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list
Cc: imx
Enable USB3 controller, phy and typec related nodes.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 87 +++++++++++++++++++
1 file changed, 87 insertions(+)
diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
index afa883389456..64f20ff44ba7 100644
--- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
+++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
@@ -6,6 +6,7 @@
/dts-v1/;
#include "imx8qxp.dtsi"
+#include <dt-bindings/usb/pd.h>
/ {
model = "Freescale i.MX8QXP MEK";
@@ -28,6 +29,21 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
+
+ gpio-sbu-mux {
+ compatible = "gpio-sbu-mux";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec_mux>;
+ select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>;
+ enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
+ orientation-switch;
+
+ port {
+ usb3_data_ss: endpoint {
+ remote-endpoint = <&typec_con_ss>;
+ };
+ };
+ };
};
&dsp {
@@ -127,6 +143,44 @@ light-sensor@44 {
};
};
};
+
+ ptn5110: tcpc@50 {
+ compatible = "nxp,ptn5110";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_typec>;
+ reg = <0x50>;
+
+ interrupt-parent = <&lsio_gpio1>;
+ interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
+ status = "okay";
+
+ port {
+ typec_dr_sw: endpoint {
+ remote-endpoint = <&usb3_drd_sw>;
+ };
+ };
+
+ usb_con1: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "source";
+ data-role = "dual";
+ source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ typec_con_ss: endpoint {
+ remote-endpoint = <&usb3_data_ss>;
+ };
+ };
+ };
+ };
+ };
+
};
&lpuart0 {
@@ -204,6 +258,27 @@ &usdhc2 {
status = "okay";
};
+&usb3_phy {
+ status = "okay";
+};
+
+&usbotg3 {
+ status = "okay";
+};
+
+&usbotg3_cdns3 {
+ dr_mode = "otg";
+ usb-role-switch;
+ status = "okay";
+
+ port {
+ usb3_drd_sw: endpoint {
+ remote-endpoint = <&typec_dr_sw>;
+ };
+ };
+};
+
+
&vpu {
compatible = "nxp,imx8qxp-vpu";
status = "okay";
@@ -267,6 +342,18 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
>;
};
+ pinctrl_typec: typecgrp {
+ fsl,pins = <
+ IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
+ >;
+ };
+
+ pinctrl_typec_mux: typecmuxgrp {
+ fsl,pins = <
+ IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
+ >;
+ };
+
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
--
2.34.1
^ permalink raw reply related [flat|nested] 4+ messages in thread* Re: [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3
2023-02-13 22:22 ` [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
@ 2023-03-14 0:53 ` Shawn Guo
0 siblings, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2023-03-14 0:53 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list, imx
On Mon, Feb 13, 2023 at 05:22:28PM -0500, Frank Li wrote:
> Enable USB3 controller, phy and typec related nodes.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> arch/arm64/boot/dts/freescale/imx8qxp-mek.dts | 87 +++++++++++++++++++
> 1 file changed, 87 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> index afa883389456..64f20ff44ba7 100644
> --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts
> @@ -6,6 +6,7 @@
> /dts-v1/;
>
> #include "imx8qxp.dtsi"
> +#include <dt-bindings/usb/pd.h>
>
> / {
> model = "Freescale i.MX8QXP MEK";
> @@ -28,6 +29,21 @@ reg_usdhc2_vmmc: usdhc2-vmmc {
> gpio = <&lsio_gpio4 19 GPIO_ACTIVE_HIGH>;
> enable-active-high;
> };
> +
> + gpio-sbu-mux {
> + compatible = "gpio-sbu-mux";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_typec_mux>;
> + select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_LOW>;
> + enable-gpios = <&pca9557_a 7 GPIO_ACTIVE_LOW>;
> + orientation-switch;
> +
> + port {
> + usb3_data_ss: endpoint {
> + remote-endpoint = <&typec_con_ss>;
> + };
> + };
> + };
> };
>
> &dsp {
> @@ -127,6 +143,44 @@ light-sensor@44 {
> };
> };
> };
> +
> + ptn5110: tcpc@50 {
> + compatible = "nxp,ptn5110";
> + pinctrl-names = "default";
> + pinctrl-0 = <&pinctrl_typec>;
> + reg = <0x50>;
> +
Unneeded newline.
> + interrupt-parent = <&lsio_gpio1>;
> + interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
> + status = "okay";
Unneeded "okay" status.
> +
> + port {
> + typec_dr_sw: endpoint {
> + remote-endpoint = <&usb3_drd_sw>;
> + };
> + };
> +
> + usb_con1: connector {
> + compatible = "usb-c-connector";
> + label = "USB-C";
> + power-role = "source";
> + data-role = "dual";
> + source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>;
> +
> + ports {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + port@1 {
> + reg = <1>;
> + typec_con_ss: endpoint {
Broken indent alignment.
Shawn
> + remote-endpoint = <&usb3_data_ss>;
> + };
> + };
> + };
> + };
> + };
> +
> };
>
> &lpuart0 {
> @@ -204,6 +258,27 @@ &usdhc2 {
> status = "okay";
> };
>
> +&usb3_phy {
> + status = "okay";
> +};
> +
> +&usbotg3 {
> + status = "okay";
> +};
> +
> +&usbotg3_cdns3 {
> + dr_mode = "otg";
> + usb-role-switch;
> + status = "okay";
> +
> + port {
> + usb3_drd_sw: endpoint {
> + remote-endpoint = <&typec_dr_sw>;
> + };
> + };
> +};
> +
> +
> &vpu {
> compatible = "nxp,imx8qxp-vpu";
> status = "okay";
> @@ -267,6 +342,18 @@ IMX8QXP_UART0_TX_ADMA_UART0_TX 0x06000020
> >;
> };
>
> + pinctrl_typec: typecgrp {
> + fsl,pins = <
> + IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021
> + >;
> + };
> +
> + pinctrl_typec_mux: typecmuxgrp {
> + fsl,pins = <
> + IMX8QXP_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60
> + >;
> + };
> +
> pinctrl_usdhc1: usdhc1grp {
> fsl,pins = <
> IMX8QXP_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support
2023-02-13 22:22 [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Frank Li
2023-02-13 22:22 ` [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
@ 2023-03-14 0:50 ` Shawn Guo
1 sibling, 0 replies; 4+ messages in thread
From: Shawn Guo @ 2023-03-14 0:50 UTC (permalink / raw)
To: Frank Li
Cc: Rob Herring, Krzysztof Kozlowski, Sascha Hauer,
Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE,
open list, imx
On Mon, Feb 13, 2023 at 05:22:27PM -0500, Frank Li wrote:
> There are cadence usb3.0 controller in 8qxp and 8qm.
> Add usb3 node at common connect subsystem.
>
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
> .../boot/dts/freescale/imx8-ss-conn.dtsi | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> index 4852760adeee..94692cee25a0 100644
> --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi
> @@ -138,6 +138,56 @@ fec2: ethernet@5b050000 {
> status = "disabled";
> };
>
> + usbotg3: usb@5b110000 {
> + compatible = "fsl,imx8qm-usb3";
Is the compatible documented?
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> + reg = <0x5b110000 0x10000>;
> + clocks = <&usb3_lpcg IMX_LPCG_CLK_1>,
> + <&usb3_lpcg IMX_LPCG_CLK_0>,
> + <&usb3_lpcg IMX_LPCG_CLK_7>,
> + <&usb3_lpcg IMX_LPCG_CLK_4>,
> + <&usb3_lpcg IMX_LPCG_CLK_5>;
> + clock-names = "usb3_lpm_clk", "usb3_bus_clk", "usb3_aclk",
> + "usb3_ipg_clk", "usb3_core_pclk";
Can we align the indent at " on above line?
> + assigned-clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
> + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
> + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
Can we align the indent at < on above line?
Shawn
> + assigned-clock-rates = <125000000>, <12000000>, <250000000>;
> + power-domains = <&pd IMX_SC_R_USB_2>;
> + status = "disabled";
> +
> + usbotg3_cdns3: usb@5b120000 {
> + compatible = "cdns,usb3";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-names = "host", "peripheral", "otg", "wakeup";
> + reg = <0x5b130000 0x10000>, /* memory area for HOST registers */
> + <0x5b140000 0x10000>, /* memory area for DEVICE registers */
> + <0x5b120000 0x10000>; /* memory area for OTG/DRD registers */
> + reg-names = "xhci", "dev", "otg";
> + phys = <&usb3_phy>;
> + phy-names = "cdns3,usb3-phy";
> + status = "disabled";
> + };
> + };
> +
> + usb3_phy: usb-phy@5b160000 {
> + compatible = "nxp,salvo-phy";
> + reg = <0x5b160000 0x40000>;
> + clocks = <&usb3_lpcg IMX_LPCG_CLK_6>;
> + clock-names = "salvo_phy_clk";
> + power-domains = <&pd IMX_SC_R_USB_2_PHY>;
> + #phy-cells = <0>;
> + status = "disabled";
> + };
> +
> /* LPCG clocks */
> sdhc0_lpcg: clock-controller@5b200000 {
> compatible = "fsl,imx8qxp-lpcg";
> @@ -234,4 +284,26 @@ usb2_lpcg: clock-controller@5b270000 {
> clock-output-names = "usboh3_ahb_clk", "usboh3_phy_ipg_clk";
> power-domains = <&pd IMX_SC_R_USB_0_PHY>;
> };
> +
> + usb3_lpcg: clock-controller@5b280000 {
> + compatible = "fsl,imx8qxp-lpcg";
> + reg = <0x5b280000 0x10000>;
> + #clock-cells = <1>;
> + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_1>,
> + <IMX_LPCG_CLK_4>, <IMX_LPCG_CLK_5>,
> + <IMX_LPCG_CLK_6>, <IMX_LPCG_CLK_7>;
> + clocks = <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_PER>,
> + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MISC>,
> + <&conn_ipg_clk>,
> + <&conn_ipg_clk>,
> + <&conn_ipg_clk>,
> + <&clk IMX_SC_R_USB_2 IMX_SC_PM_CLK_MST_BUS>;
> + clock-output-names = "usb3_app_clk",
> + "usb3_lpm_clk",
> + "usb3_ipg_clk",
> + "usb3_core_pclk",
> + "usb3_phy_clk",
> + "usb3_aclk";
> + power-domains = <&pd IMX_SC_R_USB_2_PHY>;
> + };
> };
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2023-03-14 0:53 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2023-02-13 22:22 [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Frank Li
2023-02-13 22:22 ` [PATCH 2/2] arm64: dts: freescale: imx8qxp-mek: enable cadence usb3 Frank Li
2023-03-14 0:53 ` Shawn Guo
2023-03-14 0:50 ` [PATCH 1/2] arm64: dts: imx8qxp: add cadence usb3 support Shawn Guo
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