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[83.9.29.190]) by smtp.gmail.com with ESMTPSA id x1-20020ac25dc1000000b004f64b8eee61sm2088406lfq.97.2023.06.14.04.35.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 14 Jun 2023 04:35:47 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH v2 0/7] SM6350 GPU Date: Wed, 14 Jun 2023 13:35:31 +0200 Message-Id: <20230315-topic-lagoon_gpu-v2-0-afcdfb18bb13@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAOmiWQC/32NWwqDMBAAryL5bopG+6BfvUeRstmucSFkQ6LSI t69qQfo5wwMs6pMiSmrW7WqRAtnllDAHCqFIwRHml+FlalNW7fNSU8SGbUHJxKeLs76igYsosU zWVUyC5m0TRBwLGGYvS8yJhr4vX8efeGR8yTps2+X5mf/HJZG1xouHVrCjnDAu+cASY6SnOq3b fsCrWAwX8YAAAA= To: Bjorn Andersson , Andy Gross , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , AngeloGioacchino Del Regno , Conor Dooley Cc: Marijn Suijten , Rob Herring , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Konrad Dybcio , Luca Weiss X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1686742545; l=1513; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=Zj6EKpI9LyjJLvwEHwqcCLEiQUgWc1gxPnuUuffY2/g=; b=REH0Yu7DJoufQBzafbTcHqja8hly3sLq7yU4EtTvyEhzgxq8NBvoWzl8NYb8tCbLsdhZ18DMC w8tIAtoHF9HAmmKgKM7XJ15oATMACRjPgEMqkd9qG59bVTRgDlQOPWG X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add all the required nodes for SM6350's A619 and fix up its GPUCC bindings. This has been ready for like 1.5y now, time to finally merge it as the display part will take some more time (due to the HW catalog rework). Depends on (bindings, admittedly I could have organized it better): https://lore.kernel.org/linux-arm-msm/20230314-topic-nvmem_compats-v1-0-508100c17603@linaro.org/#t Signed-off-by: Konrad Dybcio --- Changes in v2: - gpu_speed_bin@ -> gpu-speed-bin@ [3/5] - Order GPU nodes properly [4/5] - sort out the clock-names issue - throw in the dpu patch, as the driver part has been finally merged - pick up tags - Link to v1: https://lore.kernel.org/r/20230315-topic-lagoon_gpu-v1-0-a74cbec4ecfc@linaro.org --- Konrad Dybcio (7): clk: qcom: gpucc-sm6350: Introduce index-based clk lookup clk: qcom: gpucc-sm6350: Fix clock source names arm64: dts: qcom: sm6350: Add GPUCC node arm64: dts: qcom: sm6350: Add QFPROM node arm64: dts: qcom: sm6350: Add GPU nodes arm64: dts: qcom: sm6350: Fix ZAP region arm64: dts: qcom: sm6350: Add DPU1 nodes arch/arm64/boot/dts/qcom/sm6350.dtsi | 394 ++++++++++++++++++++++++++++++++++- drivers/clk/qcom/gpucc-sm6350.c | 18 +- 2 files changed, 402 insertions(+), 10 deletions(-) --- base-commit: b16049b21162bb649cdd8519642a35972b7910fe change-id: 20230315-topic-lagoon_gpu-8c2abccbc6eb Best regards, -- Konrad Dybcio