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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id zq24-20020a0568718e9800b00172721f6cd5sm3354302oab.16.2023.03.20.07.49.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 20 Mar 2023 07:49:15 -0700 (PDT) Received: (nullmailer pid 1615498 invoked by uid 1000); Mon, 20 Mar 2023 14:49:14 -0000 Date: Mon, 20 Mar 2023 09:49:14 -0500 From: Rob Herring To: Yoshihiro Shimoda Cc: joro@8bytes.org, will@kernel.org, robin.murphy@arm.com, krzysztof.kozlowski+dt@linaro.org, geert+renesas@glider.be, iommu@lists.linux.dev, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: Re: [PATCH v4] dt-bindings: iommu: renesas, ipmmu-vmsa: Update for R-Car Gen4 Message-ID: <20230320144914.GA1609519-robh@kernel.org> References: <20230313124026.954514-1-yoshihiro.shimoda.uh@renesas.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230313124026.954514-1-yoshihiro.shimoda.uh@renesas.com> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 13, 2023 at 09:40:26PM +0900, Yoshihiro Shimoda wrote: > Since R-Car Gen4 does not have the main IPMMU IMSSTR register, update > the bindings to drop the interrupt bit number from the > renesas,ipmmu-main property. Wouldn't it be easier to define a value meaning 'no interrupt bit' such as 0 or ~0 than having a variable sized property to parse? > > Signed-off-by: Yoshihiro Shimoda > [geert: Re-add removed items level, add minItems/maxItems constraints] > Signed-off-by: Geert Uytterhoeven > --- > Changes from v3: > https://lore.kernel.org/all/20230209133440.2643228-1-yoshihiro.shimoda.uh@renesas.com/ > - Revise the dt-bindings by Geert-san (Thanks a lot!). > > .../bindings/iommu/renesas,ipmmu-vmsa.yaml | 32 ++++++++++++++----- > 1 file changed, 24 insertions(+), 8 deletions(-) > > diff --git a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml > index 72308a4c14e7..be90f68c11d1 100644 > --- a/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml > +++ b/Documentation/devicetree/bindings/iommu/renesas,ipmmu-vmsa.yaml > @@ -74,16 +74,16 @@ properties: > renesas,ipmmu-main: > $ref: /schemas/types.yaml#/definitions/phandle-array > items: > - - items: > + - minItems: 1 > + items: > - description: phandle to main IPMMU > - - description: the interrupt bit number associated with the particular > - cache IPMMU device. The interrupt bit number needs to match the main > - IPMMU IMSSTR register. Only used by cache IPMMU instances. > + - description: > + The interrupt bit number associated with the particular cache > + IPMMU device. If present, the interrupt bit number needs to match > + the main IPMMU IMSSTR register. Only used by cache IPMMU > + instances. > description: > - Reference to the main IPMMU phandle plus 1 cell. The cell is > - the interrupt bit number associated with the particular cache IPMMU > - device. The interrupt bit number needs to match the main IPMMU IMSSTR > - register. Only used by cache IPMMU instances. > + Reference to the main IPMMU. > > required: > - compatible > @@ -109,6 +109,22 @@ allOf: > required: > - power-domains > > + - if: > + properties: > + compatible: > + contains: > + const: renesas,rcar-gen4-ipmmu-vmsa > + then: > + properties: > + renesas,ipmmu-main: > + items: > + - maxItems: 1 > + else: > + properties: > + renesas,ipmmu-main: > + items: > + - minItems: 2 > + > examples: > - | > #include > -- > 2.25.1 >