From: Alexandre Torgue <alexandre.torgue@foss.st.com>
To: <robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<linux@rempel-privat.de>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
<linux-stm32@st-md-mailman.stormreply.com>,
<linux-kernel@vger.kernel.org>
Subject: [PATCH] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15
Date: Mon, 20 Mar 2023 18:11:23 +0100 [thread overview]
Message-ID: <20230320171123.6263-1-alexandre.torgue@foss.st.com> (raw)
Bank A and B IOs can't be handled by the pin controller 'Z'. This patch
assign spi1 pin definition to the correct controller.
Fixes: 9ad65d245b7b ("ARM: dts: stm32: stm32mp15-pinctrl: add spi1-1 pinmux group")
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
index a9d2bec99014..e15a3b2a9b39 100644
--- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
+++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi
@@ -1880,6 +1880,21 @@
};
};
+ spi1_pins_b: spi1-1 {
+ pins1 {
+ pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
+ <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
+ bias-disable;
+ drive-push-pull;
+ slew-rate = <1>;
+ };
+
+ pins2 {
+ pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
+ bias-disable;
+ };
+ };
+
spi2_pins_a: spi2-0 {
pins1 {
pinmux = <STM32_PINMUX('B', 10, AF5)>, /* SPI2_SCK */
@@ -2448,19 +2463,4 @@
bias-disable;
};
};
-
- spi1_pins_b: spi1-1 {
- pins1 {
- pinmux = <STM32_PINMUX('A', 5, AF5)>, /* SPI1_SCK */
- <STM32_PINMUX('B', 5, AF5)>; /* SPI1_MOSI */
- bias-disable;
- drive-push-pull;
- slew-rate = <1>;
- };
-
- pins2 {
- pinmux = <STM32_PINMUX('A', 6, AF5)>; /* SPI1_MISO */
- bias-disable;
- };
- };
};
--
2.17.1
next reply other threads:[~2023-03-20 17:18 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-20 17:11 Alexandre Torgue [this message]
2023-03-28 9:39 ` [PATCH] ARM: dts: stm32: fix spi1 pin assignment on stm32mp15 Alexandre TORGUE
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