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[66.90.144.107]) by smtp.gmail.com with ESMTPSA id q132-20020acac08a000000b0037fa035f4f3sm5161798oif.53.2023.03.21.12.54.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Mar 2023 12:54:30 -0700 (PDT) Received: (nullmailer pid 1344021 invoked by uid 1000); Tue, 21 Mar 2023 19:54:29 -0000 Date: Tue, 21 Mar 2023 14:54:29 -0500 From: Rob Herring To: Abel Vesa Cc: Andy Gross , Bjorn Andersson , Konrad Dybcio , Bjorn Helgaas , Lorenzo Pieralisi , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , Krzysztof Kozlowski , Manivannan Sadhasivam , Philipp Zabel , Linux Kernel Mailing List , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, Krzysztof Kozlowski , Johan Hovold Subject: Re: [RESEND PATCH v9 1/2] dt-bindings: PCI: qcom: Add SM8550 compatible Message-ID: <20230321195429.GA1341884-robh@kernel.org> References: <20230320144658.1794991-1-abel.vesa@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230320144658.1794991-1-abel.vesa@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Mon, Mar 20, 2023 at 04:46:57PM +0200, Abel Vesa wrote: > Add the SM8550 platform to the binding. > > Signed-off-by: Abel Vesa > Reviewed-by: Krzysztof Kozlowski > Reviewed-by: Johan Hovold > --- > > This patch is a resend of the following: > https://lore.kernel.org/all/20230208180020.2761766-10-abel.vesa@linaro.org/ > > No changes since then. > > .../devicetree/bindings/pci/qcom,pcie.yaml | 40 +++++++++++++++++++ > 1 file changed, 40 insertions(+) > > diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > index fb32c43dd12d..be7b4b805291 100644 > --- a/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > +++ b/Documentation/devicetree/bindings/pci/qcom,pcie.yaml > @@ -38,6 +38,7 @@ properties: > - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550 > - items: > - const: qcom,pcie-msm8998 > - const: qcom,pcie-msm8996 > @@ -58,6 +59,12 @@ properties: > minItems: 1 > maxItems: 8 > > + iommus: > + maxItems: 1 > + > + iommu-map: > + maxItems: 2 I think this will conflict with a series from Mani. 'iommus' use is also wrong here. > + > # Common definitions for clocks, clock-names and reset. > # Platform constraints are described later. > clocks: > @@ -205,6 +212,7 @@ allOf: > - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550 > then: > properties: > reg: > @@ -639,6 +647,37 @@ allOf: > items: > - const: pci # PCIe core reset > > + - if: > + properties: > + compatible: > + contains: > + enum: > + - qcom,pcie-sm8550 > + then: > + properties: > + clocks: > + minItems: 7 > + maxItems: 8 > + clock-names: > + minItems: 7 > + items: > + - const: aux # Auxiliary clock > + - const: cfg # Configuration clock > + - const: bus_master # Master AXI clock > + - const: bus_slave # Slave AXI clock > + - const: slave_q2a # Slave Q2A clock > + - const: ddrss_sf_tbu # PCIe SF TBU clock > + - const: noc_aggr # Aggre NoC PCIe AXI clock > + - const: cnoc_sf_axi # Config NoC PCIe1 AXI clock > + resets: > + minItems: 1 > + maxItems: 2 > + reset-names: > + minItems: 1 > + items: > + - const: pci # PCIe core reset > + - const: link_down # PCIe link down reset > + > - if: > properties: > compatible: > @@ -724,6 +763,7 @@ allOf: > - qcom,pcie-sm8350 > - qcom,pcie-sm8450-pcie0 > - qcom,pcie-sm8450-pcie1 > + - qcom,pcie-sm8550 > then: > oneOf: > - properties: > -- > 2.34.1 >