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[83.9.3.225]) by smtp.gmail.com with ESMTPSA id f10-20020ac24e4a000000b004db3e330dcesm5008471lfr.178.2023.03.28.03.02.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 03:03:00 -0700 (PDT) From: Konrad Dybcio Subject: [PATCH 0/2] Resolve MPM register space situation Date: Tue, 28 Mar 2023 12:02:51 +0200 Message-Id: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAEu7ImQC/x2N0QrCMAwAf2Xk2cBsh1R/RUTaGLfA2pVmijD27 ws+3sFxGyg3YYVbt0Hjr6gsxeB86oCmWEZGeRmD653vvQu4LlUIs44t5meuGekSQmKfyF0HsCx FZUwtFposLJ95Nlkbv+X3/9wf+34ARPLR+3cAAAA= To: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Shawn Guo Cc: Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio X-Mailer: b4 0.12.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1679997779; l=1895; i=konrad.dybcio@linaro.org; s=20230215; h=from:subject:message-id; bh=lF/bvkNJ7NLlgQqY7yN7AeVawfTeX3/WEciMsVGTE3U=; b=fcbsdJo5+WcFlPqfdWkwDg2oF4yvKNoIHpAZnGXRnPm4LbzWTwVvxhKLcC5BFQOdRQ45U5uZjkeJ hcTDCb0iAdJYaWg+95rEY7hXkXk3FcpPviMvbKzTRNnaZrbl17JO X-Developer-Key: i=konrad.dybcio@linaro.org; a=ed25519; pk=iclgkYvtl2w05SSXO5EjjSYlhFKsJ+5OSZBjOkQuEms= Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The MPM (and some other things, irrelevant to this patchset) resides (as far as the ARM cores are concerned, anyway) in a MMIO-mapped region that's a portion of the RPM (low-power management core)'s RAM, known as the RPM Message RAM. Representing this relation in the Device Tree creates some challenges, as one would either have to treat a memory region as a bus, map nodes in a way such that their reg-s would be overlapping, or supply the nodes with a slice of that region. This series implements the third option, by adding a qcom,rpm-msg-ram property, which has been used for some drivers poking into this region before. Bindings ABI compatibility is preserved through keeping the "normal" (a.k.a read the reg property and map that region) way of passing the register space. Example representation with this patchset: / { [...] mpm: interrupt-controller { compatible = "qcom,mpm"; qcom,rpm-msg-ram = <&apss_mpm>; [...] }; [...] soc: soc@0 { [...] rpm_msg_ram: sram@45f0000 { compatible = "qcom,rpm-msg-ram", "mmio-sram"; reg = <0 0x045f0000 0 0x7000>; #address-cells = <1>; #size-cells = <1>; ranges = <0 0x0 0x045f0000 0x7000>; apss_mpm: sram@1b8 { reg = <0x1b8 0x48>; }; }; }; }; Signed-off-by: Konrad Dybcio --- Konrad Dybcio (2): dt-bindings: interrupt-controller: mpm: Allow passing reg through phandle irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space .../bindings/interrupt-controller/qcom,mpm.yaml | 6 ++++- drivers/irqchip/irq-qcom-mpm.c | 30 ++++++++++++++++++---- 2 files changed, 30 insertions(+), 6 deletions(-) --- base-commit: a6faf7ea9fcb7267d06116d4188947f26e00e57e change-id: 20230328-topic-msgram_mpm-c688be3bc294 Best regards, -- Konrad Dybcio