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From: Konrad Dybcio <konrad.dybcio@linaro.org>
To: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Thomas Gleixner <tglx@linutronix.de>,
	Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Shawn Guo <shawn.guo@linaro.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
	linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org,
	devicetree@vger.kernel.org,
	Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH v2 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle
Date: Wed, 05 Apr 2023 12:48:34 +0200	[thread overview]
Message-ID: <20230328-topic-msgram_mpm-v2-1-e24a48e57f0d@linaro.org> (raw)
In-Reply-To: <20230328-topic-msgram_mpm-v2-0-e24a48e57f0d@linaro.org>

Due to the wild nature of the Qualcomm RPM Message RAM, we can't really
use 'reg' to point to the MPM's slice of Message RAM without cutting into
an already-defined RPM MSG RAM node used for GLINK and SMEM.

Document passing the register space as a slice of SRAM through the
qcom,rpm-msg-ram property. This also makes 'reg' deprecated.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
 .../devicetree/bindings/interrupt-controller/qcom,mpm.yaml   | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
index 509d20c091af..61fc5b1b74dc 100644
--- a/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,mpm.yaml
@@ -29,6 +29,12 @@ properties:
     maxItems: 1
     description:
       Specifies the base address and size of vMPM registers in RPM MSG RAM.
+    deprecated: true
+
+  qcom,rpm-msg-ram:
+    $ref: /schemas/types.yaml#/definitions/phandle
+    description:
+      Phandle to the APSS MPM slice of the RPM Message RAM
 
   interrupts:
     maxItems: 1
@@ -64,23 +70,22 @@ properties:
 
 required:
   - compatible
-  - reg
   - interrupts
   - mboxes
   - interrupt-controller
   - '#interrupt-cells'
   - qcom,mpm-pin-count
   - qcom,mpm-pin-map
+  - qcom,rpm-msg-ram
 
 additionalProperties: false
 
 examples:
   - |
     #include <dt-bindings/interrupt-controller/arm-gic.h>
-    mpm: interrupt-controller@45f01b8 {
+    mpm: interrupt-controller {
         compatible = "qcom,mpm";
         interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
-        reg = <0x45f01b8 0x1000>;
         mboxes = <&apcs_glb 1>;
         interrupt-controller;
         #interrupt-cells = <2>;
@@ -93,4 +98,5 @@ examples:
                            <86 183>,
                            <90 260>,
                            <91 260>;
+        qcom,rpm-msg-ram = <&apss_mpm>;
     };

-- 
2.40.0


  reply	other threads:[~2023-04-05 10:48 UTC|newest]

Thread overview: 18+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-04-05 10:48 [PATCH v2 0/2] Resolve MPM register space situation Konrad Dybcio
2023-04-05 10:48 ` Konrad Dybcio [this message]
2023-04-05 12:22   ` [PATCH v2 1/2] dt-bindings: interrupt-controller: mpm: Pass MSG RAM slice through phandle Rob Herring
2023-04-05 13:47     ` Rob Herring
2023-04-05 13:49       ` Konrad Dybcio
2023-04-06 17:45         ` Krzysztof Kozlowski
2023-04-06 19:55           ` Konrad Dybcio
2023-04-07  7:00             ` Krzysztof Kozlowski
2023-04-07 11:36             ` Stephan Gerhold
2023-04-12 11:47               ` Konrad Dybcio
2023-04-12 11:55                 ` Krzysztof Kozlowski
2023-04-12 12:09                   ` Konrad Dybcio
2023-04-12 16:53                     ` Krzysztof Kozlowski
2023-04-12 17:06                       ` Konrad Dybcio
2023-04-13  8:50                         ` Krzysztof Kozlowski
2023-05-18 12:54                           ` Konrad Dybcio
2023-04-05 10:48 ` [PATCH v2 2/2] irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space Konrad Dybcio
2023-04-06  4:08   ` Shawn Guo

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