From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26DA3C76196 for ; Tue, 28 Mar 2023 15:41:02 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233379AbjC1PlB (ORCPT ); Tue, 28 Mar 2023 11:41:01 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:45548 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233824AbjC1Pko (ORCPT ); Tue, 28 Mar 2023 11:40:44 -0400 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 7B4A986AC; Tue, 28 Mar 2023 08:39:37 -0700 (PDT) Received: from pps.filterd (m0241204.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.17.1.19/8.17.1.19) with ESMTP id 32SE1LA6016212; Tue, 28 Mar 2023 17:38:40 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h=from : to : cc : subject : date : message-id : in-reply-to : references : mime-version : content-transfer-encoding : content-type; s=selector1; bh=eQMMwdgtbCFYg6RdDX7MRzsB4HskdJ9yFYqsMjdrGSM=; b=Lpb68G+T712ZWpf2lQ9iX6airbyfNaUsX5TDEinSF0mafdRw1gGz5ipFKdmPDCiZzZRx pwWlbxJiMq+XdDRIqBUSZX/nt0NemkHHKC/kKR65OEui038BPjtNT+g1ca0hoCRWWXGg HFHYaTtYoXCzKKC6iv51/CtaTR9ZoNbDOoddBbrzhZXzYzstM8NKm+9uGb3b1n9tWiyW MN/wLEQusQkaTyeeZFxwYBOPPcl0oOAfbFh66XrJvm7BfUNxBSbWeKlebmhfsbMwr+Gv rRmcNKc1c2i9nUKrYI+y6sQViWUCu7e+vEcLSJN1k6zcInJKtMi/292S0AhGn9e2JbZ2 bQ== Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 3pkwvsaate-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 28 Mar 2023 17:38:40 +0200 Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 32A6610002A; Tue, 28 Mar 2023 17:38:40 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node1.st.com [10.75.129.69]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2BD542194F6; Tue, 28 Mar 2023 17:38:40 +0200 (CEST) Received: from localhost (10.201.20.168) by SHFDAG1NODE1.st.com (10.75.129.69) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.17; Tue, 28 Mar 2023 17:38:39 +0200 From: Valentin Caron To: Alexandre Torgue CC: Rob Herring , Krzysztof Kozlowski , Maxime Coquelin , Valentin Caron , , , , Subject: [PATCH v2 5/6] ARM: dts: stm32: add pins for usart2/1/4/8 in stm32mp13-pinctrl Date: Tue, 28 Mar 2023 17:37:22 +0200 Message-ID: <20230328153723.498672-6-valentin.caron@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20230328153723.498672-1-valentin.caron@foss.st.com> References: <20230328153723.498672-1-valentin.caron@foss.st.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.201.20.168] X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SHFDAG1NODE1.st.com (10.75.129.69) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.254,Aquarius:18.0.942,Hydra:6.0.573,FMLib:17.11.170.22 definitions=2023-03-24_11,2023-03-28_02,2023-02-09_01 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pins for uart4, uart8, usart1 and usart2 in stm32mp13-pinctrl.dtsi Theses pins have three states: default, sleep and idle. Signed-off-by: Valentin Caron --- arch/arm/boot/dts/stm32mp13-pinctrl.dtsi | 129 +++++++++++++++++++++++ 1 file changed, 129 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi index b2dce3a29f39..27e0c3826789 100644 --- a/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp13-pinctrl.dtsi @@ -258,4 +258,133 @@ pins2 { bias-disable; }; }; + + uart4_idle_pins_a: uart4-idle-0 { + pins1 { + pinmux = ; /* UART4_TX */ + }; + pins2 { + pinmux = ; /* UART4_RX */ + bias-disable; + }; + }; + + uart4_sleep_pins_a: uart4-sleep-0 { + pins { + pinmux = , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + + uart8_pins_a: uart8-0 { + pins1 { + pinmux = ; /* UART8_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_idle_pins_a: uart8-idle-0 { + pins1 { + pinmux = ; /* UART8_TX */ + }; + pins2 { + pinmux = ; /* UART8_RX */ + bias-pull-up; + }; + }; + + uart8_sleep_pins_a: uart8-sleep-0 { + pins { + pinmux = , /* UART8_TX */ + ; /* UART8_RX */ + }; + }; + + usart1_pins_a: usart1-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART1_RX */ + ; /* USART1_CTS_NSS */ + bias-pull-up; + }; + }; + + usart1_idle_pins_a: usart1-idle-0 { + pins1 { + pinmux = , /* USART1_TX */ + ; /* USART1_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART1_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART1_RX */ + bias-pull-up; + }; + }; + + usart1_sleep_pins_a: usart1-sleep-0 { + pins { + pinmux = , /* USART1_TX */ + , /* USART1_RTS */ + , /* USART1_CTS_NSS */ + ; /* USART1_RX */ + }; + }; + + usart2_pins_a: usart2-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = , /* USART2_TX */ + ; /* USART2_CTS_NSS */ + }; + pins2 { + pinmux = ; /* USART2_RTS */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins3 { + pinmux = ; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = , /* USART2_TX */ + , /* USART2_RTS */ + , /* USART2_RX */ + ; /* USART2_CTS_NSS */ + }; + }; }; -- 2.25.1