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[80.251.214.228]) by smtp.gmail.com with ESMTPSA id bc9-20020a170902930900b001a20b31a23fsm10109449plb.293.2023.03.28.20.34.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Mar 2023 20:34:31 -0700 (PDT) Date: Wed, 29 Mar 2023 11:34:24 +0800 From: Shawn Guo To: Konrad Dybcio Cc: Andy Gross , Bjorn Andersson , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Marijn Suijten , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 0/2] Resolve MPM register space situation Message-ID: <20230329033424.GA3554086@dragon> References: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20230328-topic-msgram_mpm-v1-0-1b788a5f5a33@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Tue, Mar 28, 2023 at 12:02:51PM +0200, Konrad Dybcio wrote: > The MPM (and some other things, irrelevant to this patchset) resides > (as far as the ARM cores are concerned, anyway) in a MMIO-mapped region > that's a portion of the RPM (low-power management core)'s RAM, known > as the RPM Message RAM. Representing this relation in the Device Tree > creates some challenges, as one would either have to treat a memory > region as a bus, map nodes in a way such that their reg-s would be > overlapping, or supply the nodes with a slice of that region. > > This series implements the third option, by adding a qcom,rpm-msg-ram > property, which has been used for some drivers poking into this region > before. Bindings ABI compatibility is preserved through keeping the > "normal" (a.k.a read the reg property and map that region) way of > passing the register space. I have to admit that I wasn't aware of it, this message RAM is also accessed by cores like modem, ADSP etc. I agree in principle this is a good change! Shawn > > Example representation with this patchset: > > / { > [...] > > mpm: interrupt-controller { > compatible = "qcom,mpm"; > qcom,rpm-msg-ram = <&apss_mpm>; > [...] > }; > > [...] > > soc: soc@0 { > [...] > > rpm_msg_ram: sram@45f0000 { > compatible = "qcom,rpm-msg-ram", "mmio-sram"; > reg = <0 0x045f0000 0 0x7000>; > #address-cells = <1>; > #size-cells = <1>; > ranges = <0 0x0 0x045f0000 0x7000>; > > apss_mpm: sram@1b8 { > reg = <0x1b8 0x48>; > }; > }; > }; > }; > > Signed-off-by: Konrad Dybcio > --- > Konrad Dybcio (2): > dt-bindings: interrupt-controller: mpm: Allow passing reg through phandle > irqchip: irq-qcom-mpm: Support passing a slice of SRAM as reg space > > .../bindings/interrupt-controller/qcom,mpm.yaml | 6 ++++- > drivers/irqchip/irq-qcom-mpm.c | 30 ++++++++++++++++++---- > 2 files changed, 30 insertions(+), 6 deletions(-) > --- > base-commit: a6faf7ea9fcb7267d06116d4188947f26e00e57e > change-id: 20230328-topic-msgram_mpm-c688be3bc294 > > Best regards, > -- > Konrad Dybcio >