From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8A9D5C74A5B for ; Wed, 29 Mar 2023 21:55:20 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229605AbjC2VzT (ORCPT ); Wed, 29 Mar 2023 17:55:19 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:50102 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229510AbjC2VzS (ORCPT ); Wed, 29 Mar 2023 17:55:18 -0400 Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id BBA3797; Wed, 29 Mar 2023 14:55:16 -0700 (PDT) Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id 32TLt6au039103; Wed, 29 Mar 2023 16:55:06 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1680126906; bh=2OoQhKzka37UYBcMeeKflQjgVO0yFL0GNd1Bh9ptI4E=; h=Date:From:To:CC:Subject:References:In-Reply-To; b=IyyHzuoxNlC6chbTeDgpmuxkCLpW3F+whW+NxwBkYo0KMr4Myh84LpcoXg8wO+UIM K7FLmxSl2vg2QQA06eLjGD6mLVhTKOEphTwT8EWhDnQs0A+u8hLV0P7zi3y3eODk7u NKpEA6vyi+Cc2ybepqohfUkztDgmanc26LceR7/k= Received: from DFLE114.ent.ti.com (dfle114.ent.ti.com [10.64.6.35]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 32TLt6gk062820 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 29 Mar 2023 16:55:06 -0500 Received: from DFLE109.ent.ti.com (10.64.6.30) by DFLE114.ent.ti.com (10.64.6.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16; Wed, 29 Mar 2023 16:55:06 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DFLE109.ent.ti.com (10.64.6.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.16 via Frontend Transport; Wed, 29 Mar 2023 16:55:05 -0500 Received: from localhost (ileaxei01-snat.itg.ti.com [10.180.69.5]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 32TLt5Xk103802; Wed, 29 Mar 2023 16:55:05 -0500 Date: Wed, 29 Mar 2023 16:55:05 -0500 From: Nishanth Menon To: Hari Nagalla CC: , , , , , , Subject: Re: [PATCH 1/3] arm64: dts: ti: k3-j784s4-main: Add MAIN domain R5F cluster nodes Message-ID: <20230329215505.gxeute6pxblbw2hn@habitual> References: <20230329093627.30719-1-hnagalla@ti.com> <20230329093627.30719-2-hnagalla@ti.com> <20230329125247.w45k5fjzmcgjdyso@delicate> <48c03b5a-6557-9eee-8b85-24d72cfbfcd1@ti.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <48c03b5a-6557-9eee-8b85-24d72cfbfcd1@ti.com> X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On 15:19-20230329, Hari Nagalla wrote: [...] > >> + status = "disabled"; > > Why are these disabled by default? > Well, the idea is to let the board specific device tree enable needed remote > core nodes in *-evm/sk.dts and disable by default in SoC device tree files > by default. NAK. SoC dtsi nodes are enabled by default, the actual "disable" in a node only makes sense if that node has some dependency on board specific physical dts property - such as pinmux etc that characterizes. This is the discussion we have had and why selective muxes are enabled. CPU cores make no sense to disable by default - you could have a case where they may be efused out on a sub device variant, in which case, you are perfectly valid to disable that node in the board dts OR if the sub device variant is used on multiple boards, introduce a sub board variant and disable it in the dtsi. -- Regards, Nishanth Menon Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D