From: James Morse <james.morse@arm.com>
To: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org
Cc: Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Lorenzo Pieralisi <lpieralisi@kernel.org>,
Sudeep Holla <sudeep.holla@arm.com>,
Marc Zyngier <maz@kernel.org>,
Oliver Upton <oliver.upton@linux.dev>,
James Morse <james.morse@arm.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
Subject: [PATCH 3/6] arm64: cputype: Add new part numbers for Cortex-X3, and Neoverse-V2
Date: Thu, 30 Mar 2023 17:51:25 +0100 [thread overview]
Message-ID: <20230330165128.3237939-4-james.morse@arm.com> (raw)
In-Reply-To: <20230330165128.3237939-1-james.morse@arm.com>
New CPUs have new errata. Add the new partnumbers.
Signed-off-by: James Morse <james.morse@arm.com>
---
Cortex-X3:
https://developer.arm.com/documentation/101593/0102/?lang=en
Neoverse-V2:
https://developer.arm.com/documentation/102375/0002/?lang=en
---
arch/arm64/include/asm/cputype.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 683ca3af4084..1a2c55e172e8 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -84,6 +84,8 @@
#define ARM_CPU_PART_CORTEX_X2 0xD48
#define ARM_CPU_PART_NEOVERSE_N2 0xD49
#define ARM_CPU_PART_CORTEX_A78C 0xD4B
+#define ARM_CPU_PART_CORTEX_X3 0xD4E
+#define ARM_CPU_PART_NEOVERSE_V2 0xD4F
#define APM_CPU_PART_POTENZA 0x000
@@ -149,6 +151,8 @@
#define MIDR_CORTEX_X2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X2)
#define MIDR_NEOVERSE_N2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_N2)
#define MIDR_CORTEX_A78C MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A78C)
+#define MIDR_CORTEX_X3 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_X3)
+#define MIDR_NEOVERSE_V2 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_NEOVERSE_V2)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.39.2
next prev parent reply other threads:[~2023-03-30 16:53 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-03-30 16:51 [PATCH 0/6] arm64: errata: Disable FWB on parts with non-ARM interconnects James Morse
2023-03-30 16:51 ` [PATCH 1/6] dt-bindings: firmware: Add arm,errata-management James Morse
2023-03-30 20:50 ` Rob Herring
2023-03-31 8:29 ` Krzysztof Kozlowski
2023-03-31 16:58 ` James Morse
2023-04-03 9:15 ` Krzysztof Kozlowski
2023-04-03 12:05 ` Marc Zyngier
2023-03-31 13:46 ` Rob Herring
2023-03-31 16:58 ` James Morse
2023-04-03 15:45 ` Rob Herring
2023-04-04 15:19 ` James Morse
2023-03-30 16:51 ` [PATCH 2/6] firmware: smccc: Add support for erratum discovery API James Morse
2023-03-30 20:34 ` kernel test robot
2023-03-30 16:51 ` James Morse [this message]
2023-03-30 16:51 ` [PATCH 4/6] arm64: errata: Disable FWB on parts with non-ARM interconnects James Morse
2023-03-30 16:51 ` [PATCH 5/6] firmware: smccc: Allow errata management to be overridden by device tree James Morse
2023-03-30 20:44 ` kernel test robot
2023-03-31 17:05 ` James Morse
2023-03-30 16:51 ` [PATCH 6/6] arm64: errata: Add a commandline option to enable/disable #2701951 James Morse
2023-03-31 12:57 ` [PATCH 0/6] arm64: errata: Disable FWB on parts with non-ARM interconnects Rob Herring
2023-03-31 13:03 ` Rob Herring
2023-05-11 17:15 ` Catalin Marinas
2023-05-11 18:42 ` Marc Zyngier
2023-05-11 21:13 ` Catalin Marinas
2023-05-16 16:29 ` James Morse
2023-05-23 12:24 ` Robin Murphy
2023-05-23 10:48 ` Will Deacon
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