* [PATCH v1] dt-bindings: move cache controller bindings to a cache directory
@ 2023-03-30 17:32 Conor Dooley
2023-04-03 21:40 ` Rob Herring
0 siblings, 1 reply; 2+ messages in thread
From: Conor Dooley @ 2023-03-30 17:32 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: conor, Kunihiko Hayashi, Masami Hiramatsu, Scott Wood, Andy Gross,
Bjorn Andersson, Konrad Dybcio, Palmer Dabbelt, Paul Walmsley,
Michael Ellerman, Nicholas Piggin, Christophe Leroy, Serge Semin,
Rishabh Bhatnagar, Prakash Ranjan, Masahiro Yamada, devicetree,
linux-kernel, linux-arm-kernel, linuxppc-dev, linux-arm-msm,
linux-riscv, Conor Dooley
From: Conor Dooley <conor.dooley@microchip.com>
There's a bunch of bindings for (mostly l2) cache controllers
scattered to the four winds, move them to a common directory.
I renamed the freescale l2cache.txt file, as while that might make sense
when the parent dir is fsl, it's confusing after the move.
The two Marvell bindings have had a "marvell," prefix added to match
their compatibles.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
.../{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml | 2 +-
.../{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} | 0
Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml | 2 +-
.../{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} | 0
.../{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} | 0
.../devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml | 2 +-
.../devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml | 2 +-
.../socionext => cache}/socionext,uniphier-system-cache.yaml | 2 +-
MAINTAINERS | 2 ++
9 files changed, 7 insertions(+), 5 deletions(-)
rename Documentation/devicetree/bindings/{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml (95%)
rename Documentation/devicetree/bindings/{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} (100%)
rename Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml (99%)
rename Documentation/devicetree/bindings/{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} (100%)
rename Documentation/devicetree/bindings/{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} (100%)
rename Documentation/devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml (96%)
rename Documentation/devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml (98%)
rename Documentation/devicetree/bindings/{arm/socionext => cache}/socionext,uniphier-system-cache.yaml (96%)
diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
similarity index 95%
rename from Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml
rename to Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
index 1fca282f64a2..ec4f367bc0b4 100644
--- a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml
+++ b/Documentation/devicetree/bindings/cache/baikal,bt1-l2-ctl.yaml
@@ -2,7 +2,7 @@
# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC
%YAML 1.2
---
-$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml#
+$id: http://devicetree.org/schemas/cache/baikal,bt1-l2-ctl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Baikal-T1 L2-cache Control Block
diff --git a/Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt b/Documentation/devicetree/bindings/cache/freescale-l2cache.txt
similarity index 100%
rename from Documentation/devicetree/bindings/powerpc/fsl/l2cache.txt
rename to Documentation/devicetree/bindings/cache/freescale-l2cache.txt
diff --git a/Documentation/devicetree/bindings/arm/l2c2x0.yaml b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/arm/l2c2x0.yaml
rename to Documentation/devicetree/bindings/cache/l2c2x0.yaml
index 6b8f4d4fa580..d7840a5c4037 100644
--- a/Documentation/devicetree/bindings/arm/l2c2x0.yaml
+++ b/Documentation/devicetree/bindings/cache/l2c2x0.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/l2c2x0.yaml#
+$id: http://devicetree.org/schemas/cache/l2c2x0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM L2 Cache Controller
diff --git a/Documentation/devicetree/bindings/arm/mrvl/feroceon.txt b/Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/mrvl/feroceon.txt
rename to Documentation/devicetree/bindings/cache/marvell,feroceon-cache.txt
diff --git a/Documentation/devicetree/bindings/arm/mrvl/tauros2.txt b/Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt
similarity index 100%
rename from Documentation/devicetree/bindings/arm/mrvl/tauros2.txt
rename to Documentation/devicetree/bindings/cache/marvell,tauros2-cache.txt
diff --git a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
rename to Documentation/devicetree/bindings/cache/qcom,llcc.yaml
index 38efcad56dbd..14eb5175dac4 100644
--- a/Documentation/devicetree/bindings/arm/msm/qcom,llcc.yaml
+++ b/Documentation/devicetree/bindings/cache/qcom,llcc.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-2-Clause)
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/msm/qcom,llcc.yaml#
+$id: http://devicetree.org/schemas/cache/qcom,llcc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Last Level Cache Controller
diff --git a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
similarity index 98%
rename from Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
rename to Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
index eb6ab73c0f31..8a6a78e1a7ab 100644
--- a/Documentation/devicetree/bindings/riscv/sifive,ccache0.yaml
+++ b/Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
@@ -2,7 +2,7 @@
# Copyright (C) 2020 SiFive, Inc.
%YAML 1.2
---
-$id: http://devicetree.org/schemas/riscv/sifive,ccache0.yaml#
+$id: http://devicetree.org/schemas/cache/sifive,ccache0.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: SiFive Composable Cache Controller
diff --git a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml b/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml
similarity index 96%
rename from Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
rename to Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml
index 6096c082d56d..3196263685a3 100644
--- a/Documentation/devicetree/bindings/arm/socionext/socionext,uniphier-system-cache.yaml
+++ b/Documentation/devicetree/bindings/cache/socionext,uniphier-system-cache.yaml
@@ -1,7 +1,7 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
-$id: http://devicetree.org/schemas/arm/socionext/socionext,uniphier-system-cache.yaml#
+$id: http://devicetree.org/schemas/cache/socionext,uniphier-system-cache.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: UniPhier outer cache controller
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d5bc223f305..bbb0f252522b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -11893,6 +11893,7 @@ M: Scott Wood <oss@buserror.net>
L: linuxppc-dev@lists.ozlabs.org
S: Odd fixes
T: git git://git.kernel.org/pub/scm/linux/kernel/git/scottwood/linux.git
+F: Documentation/devicetree/bindings/cache/freescale-l2cache.txt
F: Documentation/devicetree/bindings/powerpc/fsl/
F: arch/powerpc/platforms/83xx/
F: arch/powerpc/platforms/85xx/
@@ -19073,6 +19074,7 @@ M: Conor Dooley <conor@kernel.org>
L: linux-riscv@lists.infradead.org
S: Maintained
T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/
+F: Documentation/devicetree/bindings/cache/sifive,ccache0.yaml
F: drivers/soc/sifive/
SILEAD TOUCHSCREEN DRIVER
--
2.39.2
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [PATCH v1] dt-bindings: move cache controller bindings to a cache directory
2023-03-30 17:32 [PATCH v1] dt-bindings: move cache controller bindings to a cache directory Conor Dooley
@ 2023-04-03 21:40 ` Rob Herring
0 siblings, 0 replies; 2+ messages in thread
From: Rob Herring @ 2023-04-03 21:40 UTC (permalink / raw)
To: Conor Dooley
Cc: Konrad Dybcio, Paul Walmsley, Christophe Leroy, Rishabh Bhatnagar,
Krzysztof Kozlowski, linux-arm-kernel, Kunihiko Hayashi,
Rob Herring, Conor Dooley, Masahiro Yamada, Masami Hiramatsu,
linuxppc-dev, Serge Semin, Prakash Ranjan, Palmer Dabbelt,
Nicholas Piggin, linux-kernel, Bjorn Andersson, Scott Wood,
linux-arm-msm, Andy Gross, Michael Ellerman, devicetree,
linux-riscv
On Thu, 30 Mar 2023 18:32:56 +0100, Conor Dooley wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> There's a bunch of bindings for (mostly l2) cache controllers
> scattered to the four winds, move them to a common directory.
> I renamed the freescale l2cache.txt file, as while that might make sense
> when the parent dir is fsl, it's confusing after the move.
> The two Marvell bindings have had a "marvell," prefix added to match
> their compatibles.
>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
> .../{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml | 2 +-
> .../{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} | 0
> Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml | 2 +-
> .../{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} | 0
> .../{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} | 0
> .../devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml | 2 +-
> .../devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml | 2 +-
> .../socionext => cache}/socionext,uniphier-system-cache.yaml | 2 +-
> MAINTAINERS | 2 ++
> 9 files changed, 7 insertions(+), 5 deletions(-)
> rename Documentation/devicetree/bindings/{memory-controllers => cache}/baikal,bt1-l2-ctl.yaml (95%)
> rename Documentation/devicetree/bindings/{powerpc/fsl/l2cache.txt => cache/freescale-l2cache.txt} (100%)
> rename Documentation/devicetree/bindings/{arm => cache}/l2c2x0.yaml (99%)
> rename Documentation/devicetree/bindings/{arm/mrvl/feroceon.txt => cache/marvell,feroceon-cache.txt} (100%)
> rename Documentation/devicetree/bindings/{arm/mrvl/tauros2.txt => cache/marvell,tauros2-cache.txt} (100%)
> rename Documentation/devicetree/bindings/{arm/msm => cache}/qcom,llcc.yaml (96%)
> rename Documentation/devicetree/bindings/{riscv => cache}/sifive,ccache0.yaml (98%)
> rename Documentation/devicetree/bindings/{arm/socionext => cache}/socionext,uniphier-system-cache.yaml (96%)
>
Applied, thanks!
^ permalink raw reply [flat|nested] 2+ messages in thread
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