From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CE505C6FD18 for ; Fri, 31 Mar 2023 09:16:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231737AbjCaJQN (ORCPT ); Fri, 31 Mar 2023 05:16:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37452 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231251AbjCaJQA (ORCPT ); Fri, 31 Mar 2023 05:16:00 -0400 Received: from codeconstruct.com.au (pi.codeconstruct.com.au [203.29.241.158]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E3DA61E739 for ; Fri, 31 Mar 2023 02:15:36 -0700 (PDT) Received: by codeconstruct.com.au (Postfix, from userid 10000) id 9DC10203E4; Fri, 31 Mar 2023 17:15:14 +0800 (AWST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=codeconstruct.com.au; s=2022a; t=1680254114; bh=4i6zbPriP30VDqxbtLw8DULJL2d8uZhDMuiqyIgkVgY=; h=From:To:Cc:Subject:Date:In-Reply-To:References; b=llF+FE5l2BTyEOtFdJl1ZHwWFVvFUruhmn50cOTFqKwvroSsYIYR3jOcgxj9o27gg 5SJiv06viDhRw3SPrdDRDyQ2OILIRaIMp80XtSzZbU6YiWBf/OQ7PGS/xLpj7/X+CQ RfhUiynEx2JxXgsbz8dgz8/ipMoLjuJ1esyUTVlTVPJ7g6O3ED3KDtQSEj/orsHY6v 7fbUSswN0vE0YCfxGeNdTkrJ3mR/HX6+t5AsFci+VUGc6o5ZmB6bKpAN9PR1UBWF/F +jPv8qQfT8Ru9Vq6WY6lyAfE00tv2X3rX0IFmNCxswOwUv4WB0kmO+RiLwoop59wvA ILzrdfHa7c9Dg== From: Jeremy Kerr To: linux-i3c@lists.infradead.org Cc: devicetree@vger.kernel.org, linux-aspeed@lists.ozlabs.org, Matt Johnston , Vitor Soares , Rob Herring , Krzysztof Kozlowski , Alexandre Belloni , Jack Chen , Billy Tsai , Dylan Hung , Joel Stanley , Andrew Jeffery Subject: [PATCH v3 2/3] dt-bindings: i3c: Add AST2600 i3c controller Date: Fri, 31 Mar 2023 17:15:00 +0800 Message-Id: <20230331091501.3800299-3-jk@codeconstruct.com.au> X-Mailer: git-send-email 2.39.1 In-Reply-To: <20230331091501.3800299-1-jk@codeconstruct.com.au> References: <20230331091501.3800299-1-jk@codeconstruct.com.au> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add a devicetree binding for the ast2600 i3c controller hardware. This is heavily based on the designware i3c core, plus a reset facility and two platform-specific properties: - sda-pullup-ohms: to specify the value of the configurable pullup resistors on the SDA line - aspeed,global-regs: to reference the (ast2600-specific) i3c global register block, and the device index to use within it. Reviewed-by: Krzysztof Kozlowski (on v1) Signed-off-by: Jeremy Kerr --- v2: - example: replace aspeed clock defines with constants, so we're not reliant on recent clk patches. --- .../bindings/i3c/aspeed,ast2600-i3c.yaml | 72 +++++++++++++++++++ 1 file changed, 72 insertions(+) create mode 100644 Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml diff --git a/Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml b/Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml new file mode 100644 index 000000000000..fcc3dbff9c9a --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/aspeed,ast2600-i3c.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/aspeed,ast2600-i3c.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED AST2600 i3c controller + +maintainers: + - Jeremy Kerr + +allOf: + - $ref: i3c.yaml# + +properties: + compatible: + const: aspeed,ast2600-i3c + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + sda-pullup-ohms: + enum: [545, 750, 2000] + default: 2000 + description: | + Value to configure SDA pullup resistor, in Ohms. + + aspeed,global-regs: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to i3c global register syscon node + - description: index of this i3c controller in the global register set + description: | + A (phandle, controller index) reference to the i3c global register set + used for this device. + +required: + - compatible + - reg + - clocks + - interrupts + - aspeed,global-regs + +unevaluatedProperties: false + +examples: + - | + #include + + i3c-master@2000 { + compatible = "aspeed,ast2600-i3c"; + reg = <0x2000 0x1000>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&syscon 0>; + resets = <&syscon 0>; + aspeed,global-regs = <&i3c_global 0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i3c1_default>; + interrupts = ; + }; +... -- 2.39.1