[PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'

[PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'

[Fabio Estevam]

From: Fabio Estevam <festevam@denx.de>

The Samsung DSIM IP block allows the inversion of the clock and
data lanes.

Add an optional property called 'lane-polarities' that describes the
polarities of the MIPI DSI clock and data lanes.

This property is useful for properly describing the hardware when the
board designer decided to switch the polarities of the MIPI DSI
clock and/or data lanes.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---
Changes since v1:
- Rebased against drm-misc-next that has samsung,mipi-dsim.yaml.

 .../display/bridge/samsung,mipi-dsim.yaml     | 29 +++++++++++++++++++
 1 file changed, 29 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
index e841659e20cd..04eb440ade72 100644
--- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
+++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
@@ -105,6 +105,35 @@ properties:
           DSI output port node to the panel or the next bridge
           in the chain.
 
+        properties:
+          endpoint:
+            $ref: /schemas/graph.yaml#/$defs/endpoint-base
+            unevaluatedProperties: false
+
+            properties:
+              data-lanes:
+                oneOf:
+                  - minItems: 1
+                    maxItems: 4
+                    uniqueItems: true
+                    items:
+                      enum: [ 1, 2, 3, 4 ]
+                    description:
+                      See ../../media/video-interfaces.yaml for details.
+
+              lane-polarities:
+                minItems: 1
+                maxItems: 5
+                items:
+                  enum: [ 0, 1 ]
+                description:
+                  See ../../media/video-interfaces.yaml for details.
+                  The Samsung MIPI DSI IP requires that all the data lanes have
+                  the same polarity.
+
+            dependencies:
+              lane-polarities: [data-lanes]
+
 required:
   - clock-names
   - clocks
-- 
2.34.1

[PATCH v2 2/2] drm: bridge: samsung-dsim: Implement support for clock/data polarity swap

[Fabio Estevam]

From: Marek Vasut <marex@denx.de>

Implement support for DSI clock and data lane DN/DP polarity swap by
means of decoding 'lane-polarities' DT property. The controller does
support DN/DP swap of clock lane and all data lanes, the controller
does not support polarity swap of individual data lane bundles, add
a check which verifies all data lanes have the same polarity.

This has been validated on an imx8mm board that actually has the MIPI DSI
clock lanes inverted.

Signed-off-by: Marek Vasut <marex@denx.de>
Signed-off-by: Fabio Estevam <festevam@denx.de>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
---
Changes since v1:
- Use 'drm: bridge: samsung-dsim:' as prefix (Jagan).
- Collected Jagan's Reviewed-by tag.

 drivers/gpu/drm/bridge/samsung-dsim.c | 27 ++++++++++++++++++++++++++-
 include/drm/bridge/samsung-dsim.h     |  2 ++
 2 files changed, 28 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/bridge/samsung-dsim.c b/drivers/gpu/drm/bridge/samsung-dsim.c
index e0a402a85787..5791148e2da2 100644
--- a/drivers/gpu/drm/bridge/samsung-dsim.c
+++ b/drivers/gpu/drm/bridge/samsung-dsim.c
@@ -183,6 +183,8 @@
 #define DSIM_AFC_CTL(x)			(((x) & 0x7) << 5)
 
 /* DSIM_PLLCTRL */
+#define DSIM_PLL_DPDNSWAP_CLK		(1 << 25)
+#define DSIM_PLL_DPDNSWAP_DAT		(1 << 24)
 #define DSIM_FREQ_BAND(x)		((x) << 24)
 #define DSIM_PLL_EN			BIT(23)
 #define DSIM_PLL_P(x, offset)		((x) << (offset))
@@ -622,6 +624,11 @@ static unsigned long samsung_dsim_set_pll(struct samsung_dsim *dsi,
 		reg |= DSIM_FREQ_BAND(band);
 	}
 
+	if (dsi->swap_dn_dp_clk)
+		reg |= DSIM_PLL_DPDNSWAP_CLK;
+	if (dsi->swap_dn_dp_data)
+		reg |= DSIM_PLL_DPDNSWAP_DAT;
+
 	samsung_dsim_write(dsi, DSIM_PLLCTRL_REG, reg);
 
 	timeout = 1000;
@@ -1696,7 +1703,9 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 {
 	struct device *dev = dsi->dev;
 	struct device_node *node = dev->of_node;
-	int ret;
+	u32 lane_polarities[5] = { 0 };
+	struct device_node *endpoint;
+	int i, nr_lanes, ret;
 
 	ret = samsung_dsim_of_read_u32(node, "samsung,pll-clock-frequency",
 				       &dsi->pll_clk_rate);
@@ -1713,6 +1722,22 @@ static int samsung_dsim_parse_dt(struct samsung_dsim *dsi)
 	if (ret < 0)
 		return ret;
 
+	endpoint = of_graph_get_endpoint_by_regs(node, 1, -1);
+	nr_lanes = of_property_count_u32_elems(endpoint, "data-lanes");
+	if (nr_lanes > 0 && nr_lanes <= 4) {
+		/* Polarity 0 is clock lane, 1..4 are data lanes. */
+		of_property_read_u32_array(endpoint, "lane-polarities",
+					   lane_polarities, nr_lanes + 1);
+		for (i = 1; i <= nr_lanes; i++) {
+			if (lane_polarities[1] != lane_polarities[i])
+				DRM_DEV_ERROR(dsi->dev, "Data lanes polarities do not match");
+		}
+		if (lane_polarities[0])
+			dsi->swap_dn_dp_clk = true;
+		if (lane_polarities[1])
+			dsi->swap_dn_dp_data = true;
+	}
+
 	return 0;
 }
 
diff --git a/include/drm/bridge/samsung-dsim.h b/include/drm/bridge/samsung-dsim.h
index ba5484de2b30..6a37d1e079bf 100644
--- a/include/drm/bridge/samsung-dsim.h
+++ b/include/drm/bridge/samsung-dsim.h
@@ -95,6 +95,8 @@ struct samsung_dsim {
 	u32 mode_flags;
 	u32 format;
 
+	bool swap_dn_dp_clk;
+	bool swap_dn_dp_data;
 	int state;
 	struct drm_property *brightness;
 	struct completion completed;
-- 
2.34.1

Re: [PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'

[Rob Herring]

On Thu, Apr 06, 2023 at 04:03:53PM -0300, Fabio Estevam wrote:
> From: Fabio Estevam <festevam@denx.de>
> 
> The Samsung DSIM IP block allows the inversion of the clock and
> data lanes.
> 
> Add an optional property called 'lane-polarities' that describes the
> polarities of the MIPI DSI clock and data lanes.
> 
> This property is useful for properly describing the hardware when the
> board designer decided to switch the polarities of the MIPI DSI
> clock and/or data lanes.
> 
> Signed-off-by: Fabio Estevam <festevam@denx.de>
> ---
> Changes since v1:
> - Rebased against drm-misc-next that has samsung,mipi-dsim.yaml.
> 
>  .../display/bridge/samsung,mipi-dsim.yaml     | 29 +++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> index e841659e20cd..04eb440ade72 100644
> --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml
> @@ -105,6 +105,35 @@ properties:
>            DSI output port node to the panel or the next bridge
>            in the chain.
>  
> +        properties:
> +          endpoint:
> +            $ref: /schemas/graph.yaml#/$defs/endpoint-base

No, this should be video-interfaces.yaml since you use properties from 
it.

> +            unevaluatedProperties: false
> +
> +            properties:
> +              data-lanes:
> +                oneOf:
> +                  - minItems: 1
> +                    maxItems: 4
> +                    uniqueItems: true
> +                    items:
> +                      enum: [ 1, 2, 3, 4 ]

The h/w really supports any combination of lanes to be used?

> +                    description:
> +                      See ../../media/video-interfaces.yaml for details.
> +
> +              lane-polarities:
> +                minItems: 1
> +                maxItems: 5
> +                items:
> +                  enum: [ 0, 1 ]
> +                description:
> +                  See ../../media/video-interfaces.yaml for details.
> +                  The Samsung MIPI DSI IP requires that all the data lanes have
> +                  the same polarity.

Sounds like a constraint:

oneOf:
  - items:
      const: 0
  - items:
      const: 1

> +
> +            dependencies:
> +              lane-polarities: [data-lanes]
> +
>  required:
>    - clock-names
>    - clocks
> -- 
> 2.34.1
> 

Re: [PATCH v2 1/2] dt-bindings: samsung,mipi-dsim: Add 'lane-polarities'

[Fabio Estevam]

Hi Rob,

On 12/04/2023 11:43, Rob Herring wrote:

> No, this should be video-interfaces.yaml since you use properties from
> it.

Ok, will change it.

> 
>> +            unevaluatedProperties: false
>> +
>> +            properties:
>> +              data-lanes:
>> +                oneOf:
>> +                  - minItems: 1
>> +                    maxItems: 4
>> +                    uniqueItems: true
>> +                    items:
>> +                      enum: [ 1, 2, 3, 4 ]
> 
> The h/w really supports any combination of lanes to be used?

The MIPI DSIM IP supports the usage of 1, 2, 3, or 4 data lanes.

The following cases are possible:

data-lanes = <1>;
data-lanes = <1 2>;
data-lanes = <1 2 3>;
data-lanes = <1 2 3 4>;

Lane reordering is not supported.

> 
>> +                    description:
>> +                      See ../../media/video-interfaces.yaml for 
>> details.
>> +
>> +              lane-polarities:
>> +                minItems: 1
>> +                maxItems: 5
>> +                items:
>> +                  enum: [ 0, 1 ]
>> +                description:
>> +                  See ../../media/video-interfaces.yaml for details.
>> +                  The Samsung MIPI DSI IP requires that all the data 
>> lanes have
>> +                  the same polarity.
> 
> Sounds like a constraint:
> 
> oneOf:
>   - items:
>       const: 0
>   - items:
>       const: 1

Imagine a board that has 4 data lanes and only the clock lane is 
inverted.

The representation is (the first entry is the clock lane, followed by 
the 4 data lanes):

lane-polarities = <1 0 0 0 0>;

If the board has no inversion on the clock lane, and has the data lanes 
inverted:

lane-polarities = <0 1 1 1 1>;

Should I keep the data-lanes and lane-polarities description as in this 
patch?

Please advise.

Thanks,

Fabio Estevam