Re: [PATCH v1 3/3] riscv: dts: starfive: Add cpu scaling for JH7110 SoC

[Conor Dooley <conor.dooley@microchip.com>]

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Hey Mason,

On Tue, Apr 11, 2023 at 04:32:57PM +0800, Mason Huo wrote:
> Add the operating-points-v2 to support cpu scaling
> on StarFive JH7110 SoC.

(btw, there's no need to wrap commit messages at 52 columns, you have
72 to work with)

> It supports up to 4 cpu frequency loads.
> 
> Signed-off-by: Mason Huo <mason.huo@starfivetech.com>
> ---
>  .../jh7110-starfive-visionfive-2.dtsi         | 25 +++++++++++++++++++
>  arch/riscv/boot/dts/starfive/jh7110.dtsi      | 25 +++++++++++++++++++
>  2 files changed, 50 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> index df582bddae4b..ae446b268e78 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi
> @@ -228,3 +228,28 @@ &uart0 {
>  	pinctrl-0 = <&uart0_pins>;
>  	status = "okay";
>  };
> +
> +&U74_1 {
> +	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names = "cpu";
> +	cpu-supply = <&reg_dcdc2>;
> +};
> +
> +&U74_2 {
> +	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names = "cpu";
> +	cpu-supply = <&reg_dcdc2>;
> +};
> +
> +&U74_3 {
> +	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
> +	clock-names = "cpu";
> +	cpu-supply = <&reg_dcdc2>;
> +};
> +
> +&U74_4 {
> +	clocks =  <&syscrg JH7110_SYSCLK_CPU_CORE>;
                ^^
There's a double space in each of these.

> +	clock-names = "cpu";
> +	cpu-supply = <&reg_dcdc2>;
> +};

How come these two clock properties are being added in <board>.dtsi?
Should they not be in <soc>.dtsi?

Thanks,
Conor.

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